SBASAS7 August   2024 AMC0106M05

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information (DEN Package)
    5. 5.5 Package Characteristics
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Input
      2. 6.3.2 Modulator
      3. 6.3.3 Isolation Channel Signal Transmission
      4. 6.3.4 Digital Output
        1. 6.3.4.1 Output Behavior in Case of a Full-Scale Input
        2. 6.3.4.2 Output Behavior in Case of a Missing High-Side Supply
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Shunt Resistor Sizing
        2. 7.2.2.2 Input Filter Design
        3. 7.2.2.3 Bitstream Filtering
        4. 7.2.2.4 Designing the Bootstrap Supply
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Switching Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tH DOUT hold time after rising edge of CLKIN CLOAD = 15pF 10 ns
tD Rising edge of CLKIN to DOUT valid delay CLOAD = 15pF 35 ns
tr DOUT rise time 10% to 90%, 2.7V ≤ DVDD ≤ 3.6V, CLOAD = 15pF 3.8 7 ns
10% to 90%, 4.5V ≤ DVDD ≤ 5.5V, CLOAD = 15pF 4.3 7
tf DOUT fall time 10% to 90%, 2.7V ≤ DVDD ≤ 3.6V, CLOAD = 15pF 3.8 7 ns
10% to 90%, 4.5V ≤ DVDD ≤ 5.5V, CLOAD = 15pF 4.3 7
tSTART Device start-up time AVDD step from 0  to 3.0V with AVDD ≥ 2.7V to bitstream valid, 0.1% settling 0.5 ms