AMC1304x-Q1 High-Precision, Reinforced Isolated Delta-Sigma Modulators with LDO
- SBAS799 February 2017 AMC1304L05-Q1 , AMC1304L25-Q1 , AMC1304M05-Q1 , AMC1304M25-Q1
  
  PRODUCTION DATA.

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DATA SHEET

AMC1304x-Q1 High-Precision, Reinforced Isolated Delta-Sigma Modulators with LDO

1 Features

Qualified for Automotive Applications
AEC-Q100 Qualified with the Following Results:
- Temperature Grade 1: –40°C to +125°C
- HBM ESD Classification Level 2
- CDM ESD Classification Level C6
Pin-Compatible Family with:
- ±50-mV or ±250-mV Input Voltage Ranges
- CMOS or LVDS Digital Interface Options
Excellent DC Performance:
- Offset Error: ±50 µV or ±100 µV (max)
- Offset Drift: 1.3 µV/°C (max)
- Gain Error: ±0.2% or ±0.3% (max)
- Gain Drift: ±40 ppm/°C (max)
Safety-Related Certifications:
- 7000-V_PK Reinforced Isolation per DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
- 5000-V_RMS Isolation for 1 Minute per UL1577
- CAN/CSA No. 5A-Component Acceptance Service Notice
Transient Immunity: 15 kV/µs (min)
High Electromagnetic Field Immunity
(see Application Note SLLA181A)
External 5-MHz to 20-MHz Clock Input
On-Chip 18-V LDO Regulator

2 Applications

Shunt-Based Current Sensing or Resistor-Divider-Based Voltage Sensing In:
- Traction Inverters
- Onboard Chargers (OBC)
- DC-DC Converters
- Battery Management Systems (BMS)

3 Description

The AMC1304-Q1 is a precision, delta-sigma (ΔΣ) modulator with the output separated from the input circuitry by a capacitive double isolation barrier that is highly resistant to magnetic interference. This barrier is certified to provide reinforced isolation of up to 7000 V_PEAK according to the DIN V VDE V 0884-10, UL1577 and CSA standards. Used in conjunction with isolated power supplies, the device prevents noise currents on a high common-mode voltage line from entering the local system ground and interfering with or damaging low voltage circuitry.

The input of the AMC1304-Q1 is optimized for direct connection to shunt resistors or other low voltage-level signal sources. The unique low input voltage range of the ±50-mV device allows significant reduction of the power dissipation through the shunt while supporting excellent ac and dc performance. By using an appropriate digital filter (that is, as integrated on the TMS320F2807x or TMS320F2837x families) to decimate the bit stream, the device can achieve 16 bits of resolution with a dynamic range of 81 dB (13.2 ENOB) at a data rate of 78 kSPS.

On the high-side, the modulator is supplied by an integrated low-dropout (LDO) regulator that allows an unregulated input voltage between 4 V and 18 V (LDOIN). The isolated digital interface operates from a 3.3-V or 5-V power supply (DVDD).

The AMC1304-Q1 is available in a wide-body SOIC-16 (DW) package.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
AMC1304x-Q1	SOIC (16)	10.30 mm × 7.50 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 ai_sch_bas799.gif

4 Revision History

DATE	REVISION	NOTES
February 2017	*	Initial release.

5 Device Comparison Table

DEVICE	INPUT VOLTAGE RANGE	DIFFERENTIAL INPUT RESISTANCE	DIGITAL OUTPUT INTERFACE
AMC1304L05-Q1	±50 mV	5 kΩ	LVDS
AMC1304L25-Q1	±250 mV	25 kΩ	LVDS
AMC1304M05-Q1	±50 mV	5 kΩ	CMOS
AMC1304M25-Q1	±250 mV	25 kΩ	CMOS

6 Pin Configurations and Functions

DW Package: LVDS Interface Versions (AMC1304Lx-Q1)

16-Pin SOIC

Top View

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 po_LVDS_bas655.gif

DW Package: CMOS Interface Versions (AMC1304Mx-Q1)

16-Pin SOIC

Top View

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 po_CMOS_bas655.gif

Pin Functions

PIN			I/O	DESCRIPTION
NAME	NO.
NAME	AMC1304Lx-Q1 (LVDS)	AMC1304Mx-Q1 (CMOS)
AGND	4	4	—	This pin is internally connected to pin 8 and can be left unconnected or tied to high-side ground
AGND	8	8	—	High-side ground reference
AINN	3	3	I	Inverting analog input
AINP	2	2	I	Noninverting analog input
CLKIN	13	13	I	Modulator clock input, 5 MHz to 20.1 MHz
CLKIN_N	12	—	I	Inverted modulator clock input
DGND	9, 16	9, 16	—	Controller-side ground reference
DOUT	11	11	O	Modulator data output
DOUT_N	10	—	O	Inverted modulator data output
DVDD	14	14	—	Controller-side power supply, 3.0 V to 5.5 V. See the Power-Supply Recommendations section for decoupling recommendations.
LDOIN	6	6	—	Low dropout regulator input, 4 V to 18 V
NC	1	1	—	This pin can be connected to VCAP or left unconnected
	5	5	—	This pin can be left unconnected or tied to AGND only
	—	10, 12	—	These pins have no internal connection
	15	15	—	This pin can be left unconnected or tied to DVDD only
VCAP	7	7	—	LDO output. See the Power-Supply Recommendations section for decoupling recommendations.

7 Specifications

7.1 Absolute Maximum Ratings

over the operating ambient temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage	DVDD to DGND	–0.3	6.5	V
LDO input voltage	LDOIN to AGND	–0.3	26	V
Analog input voltage at AINP, AINN		AGND – 6	3.7	V
Digital input voltage at CLKIN, CLKIN_N		DGND – 0.3	DVDD + 0.3	V
Input current to any pin except supply pins		–10	10	mA
Junction temperature, T_J			150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per AEC Q100-002⁽¹⁾	±2500	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per AEC Q100-011	±1000	V

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
LDOIN	LDO input supply voltage (LDOIN pin)	4.0	15.0	18.0	V
DVDD	Digital (controller-side) supply voltage (DVDD pin)	3.0	3.3	5.5	V
T_A	Operating ambient temperature range	–40		125	°C

7.4 Thermal Information

THERMAL METRIC ⁽¹⁾		AMC1304x-Q1	UNIT
		DW (SOIC)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	80.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	40.5	°C/W
R_θJB	Junction-to-board thermal resistance	45.1	°C/W
ψ_JT	Junction-to-top characterization parameter	11.9	°C/W
ψ_JB	Junction-to-board characterization parameter	44.5	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Power Ratings

PARAMETER		TEST CONDITIONS	VALUE	UNIT
P_D	Maximum power dissipation (both sides)	LDOIN = 18 V, DVDD = 5.5 V	161	mW
P_D1	Maximum power dissipation (high-side supply)	LDOIN = 18 V	117	mW
P_D2	Maximum power dissipation (low-side supply)	DVDD = 5.5 V, LVDS, R_LOAD = 100 Ω	44	mW

7.6 Insulation Specifications

PARAMETER		TEST CONDITIONS	VALUE	UNIT
GENERAL
CLR	Minimum air gap (clearance)⁽¹⁾	Shortest pin-to-pin distance through air	≥ 8	mm
CPG	Minimum external tracking (creepage)⁽¹⁾	Shortest pin-to-pin distance across the package surface	≥ 8	mm
DTI	Distance through insulation	Minimum internal gap (internal clearance) of the double insulation (2 × 0.0135 mm)	0.027	mm
CTI	Comparative tracking index	DIN EN 60112 (VDE 0303-11); IEC 60112	≥ 600	V
	Material group	According to IEC 60664-1	I
	Overvoltage category per IEC 60664-1	Rated mains voltage ≤ 300 V_RMS	I-IV
		Rated mains voltage ≤ 600 V_RMS	I-III
		Rated mains voltage ≤ 1000 V_RMS	I-II
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12⁽²⁾
V_IORM	Maximum repetitive peak isolation voltage	At ac voltage (bipolar or unipolar)	1414	V_PK
V_IOWM	Maximum-rated isolation working voltage	At ac voltage (sine wave)	1000	V_RMS
V_IOWM	Maximum-rated isolation working voltage	At dc voltage	1500	V_DC
V_IOTM	Maximum transient isolation voltage	V_TEST = V_IOTM, t = 60 s (qualification test)	7000	V_PK
V_IOTM	Maximum transient isolation voltage	V_TEST = 1.2 x V_IOTM, t = 1 s (100% production test)	8400	V_PK
V_IOSM	Maximum surge isolation voltage⁽³⁾	Test method per IEC 60065, 1.2/50-μs waveform, V_TEST = 1.6 x V_IOSM = 10000 V_PK (qualification)	6250	V_PK
q_pd	Apparent charge⁽⁴⁾	Method a, after input/output safety test subgroup 2 / 3, V_ini = V_IOTM, t_ini = 60 s, V_pd(m) = 1.2 x V_IORM = 1697 V_PK, t_m = 10 s	≤ 5	pC
		Method a, after environmental tests subgroup 1, V_ini = V_IOTM, t_ini = 60 s, V_pd(m) = 1.6 x V_IORM = 2263 V_PK, t_m = 10 s	≤ 5	pC
		Method b1, at routine test (100% production) and preconditioning (type test), V_ini = V_IOTM, t_ini = 1 s, V_pd(m) = 1.875 x V_IORM = 2652 V_PK, t_m = 1 s	≤ 5	pC
C_IO	Barrier capacitance, input to output⁽⁵⁾	V_IO = 0.5 V_PP at 1 MHz	1.2	pF
R_IO	Insulation resistance, input to output⁽⁵⁾	V_IO = 500 V at T_S = 150°C	> 10⁹	Ω
	Pollution degree		2
	Climatic category		40/125/21
UL1577
V_ISO	Withstand isolation voltage	V_TEST = V_ISO = 5000 V_RMS or 7000 V_DC, t = 60 s (qualification test), V_TEST = 1.2 x V_ISO = 6000 V_RMS, t = 1 s (100% production test)	5000	V_RMS

(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves or ribs on the PCB are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier are tied together, creating a two-pin device.

7.7 Safety-Related Certifications

VDE		UL
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12, DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and DIN EN 60095 (VDE 0860): 2005-11		Recognized under UL1577 component recognition and CSA component acceptance NO 5 programs
Reinforced insulation		Single protection
File number: 40040142		File number: E181974

7.8 Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output (I/O) circuitry. A failure of the I/O circuitry may allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.

PARAMETER		TEST CONDITIONS	MAX	UNIT
I_S	Safety input, output, or supply current	θ_JA = 80.2°C/W, LDOIN = 18 V, T_J = 150°C, T_A = 25°C, see Figure 3	86.5	mA
P_S	Safety input, output, or total power	θ_JA = 80.2°C/W, T_J = 150°C, T_A = 25°C, see Figure 4	1558⁽¹⁾	mW
T_S	Maximum safety temperature		150	°C

(1) Input, output, or the sum of input and output power must not exceed this value.

The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

7.9 Electrical Characteristics: AMC1304x05-Q1

All minimum and maximum specifications are at T_A = –40°C to 125°C, LDOIN = 4.0 V to 18.0 V, DVDD = 3.0 V to 5.5 V, AINP = –50 mV to 50 mV, AINN = 0 V, and sinc³ filter with OSR = 256, unless otherwise noted. Typical values are at T_A = 25°C, CLKIN = 20 MHz, LDOIN = 15.0 V, and DVDD = 3.3 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUTS
V_Clipping	Maximum differential voltage input range (AINP-AINN)			±62.5		mV
FSR	Specified linear full-scale range (AINP-AINN)		–50		50	mV
V_CM	Operating common-mode input range		–0.032		1.2	V
C_ID	Differential input capacitance			2		pF
I_IB	Input bias current	Inputs shorted to AGND	–97	–72	–57	μA
R_ID	Differential input resistance			5		kΩ
I_IO	Input offset current			±5		nA
CMTI	Common-mode transient immunity		15			kV/μs
CMRR	Common-mode rejection ratio	f_IN = 0 Hz, V_{CM min} ≤ V_IN ≤ V_{CM max}		–98		dB
CMRR	Common-mode rejection ratio	f_IN from 0.1 Hz to 50 kHz, V_{CM min} ≤ V_IN ≤ V_{CM max}		–85		dB
BW	Input bandwidth			800		kHz
DC ACCURACY
DNL	Differential nonlinearity	Resolution: 16 bits	–0.99		0.99	LSB
INL	Integral nonlinearity ⁽¹⁾	Resolution: 16 bits	–5	±1.5	5	LSB
E_O	Offset error	Initial, at 25°C	–50	±2.5	50	µV
TCE_O	Offset error thermal drift ⁽²⁾		–1.3		1.3	μV/°C
E_G	Gain error	Initial, at 25°C	–0.3%	–0.02%	0.3%
TCE_G	Gain error thermal drift ⁽³⁾		–40	±20	40	ppm/°C
PSRR	Power-supply rejection ratio	LDOIN from 4 V to 18 V, at dc		–110		dB
PSRR	Power-supply rejection ratio	LDOIN from 4 V to 18 V, from 0.1 Hz to 50 kHz		–110		dB
AC ACCURACY
SNR	Signal-to-noise ratio	f_IN = 1 kHz	76	81.5		dB
SINAD	Signal-to-noise + distortion	f_IN = 1 kHz	76	81		dB
THD	Total harmonic distortion	f_IN = 1 kHz		–90	–81	dB
SFDR	Spurious-free dynamic range	f_IN = 1 kHz	81	90		dB
DIGITAL INPUTS/OUTPUTS
External Clock
f_CLKIN	Input clock frequency		5	20	20.1	MHz
Duty_CLKIN	Duty cycle	5 MHz ≤ f_CLKIN ≤ 20.1 MHz	40%	50%	60%
CMOS Logic Family (AMC1304M05-Q1, CMOS with Schmitt Trigger)
I_IN	Input current	DGND ≤ V_IN ≤ DVDD	–1		1	μA
C_IN	Input capacitance			5		pF
V_IH	High-level input voltage		0.7 × DVDD		DVDD + 0.3	V
V_IL	Low-level input voltage		–0.3		0.3 × DVDD	V
C_LOAD	Output load capacitance	f_CLKIN = 20 MHz		30		pF
V_OH	High-level output voltage	I_OH = –20 µA	DVDD – 0.1			V
V_OH	High-level output voltage	I_OH = –4 mA	DVDD – 0.4			V
V_OL	Low-level output voltage	I_OL = 20 µA			0.1	V
V_OL	Low-level output voltage	I_OL = 4 mA			0.4	V
LVDS Logic Family (AMC1304L05-Q1)⁽⁴⁾
V_T	Differential output voltage	R_LOAD = 100 Ω	250	350	450	mV
V_OC	Common-mode output voltage		1.125	1.23	1.375	V
V_ID	Differential input voltage		100	350	600	mV
V_IC	Common-mode input voltage	V_ID = 100 mV	0.05	1.25	3.25	V
I_I	Receiver input current	DGND ≤ V_IN ≤ 3.3 V	–24	0	20	µA
POWER SUPPLY
LDOIN	LDOIN pin input voltage		4.0	15.0	18.0	V
VCAP	VCAP pin voltage			3.45		V
I_LDOIN	LDOIN pin input current			5.3	6.5	mA
DVDD	Controller-side supply voltage		3.0	3.3	5.5	V
I_DVDD	Controller-side supply current	LVDS, R_LOAD = 100 Ω		6.1	8	mA
		CMOS, 3.0 V ≤ DVDD ≤ 3.6 V, C_LOAD = 5 pF		2.7	4.0
		CMOS, 4.5 V ≤ DVDD ≤ 5.5 V, C_LOAD = 5 pF		3.2	5.5

(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as a number of LSBs or as a percent of the specified linear full-scale range (FSR).

(2) Offset error drift is calculated using the box method, as described by the following equation:
AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 ec_eodrift_bas654.gif

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 ec_eodrift_bas654.gif

(3) Gain error drift is calculated using the box method, as described by the following equation:
AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 ec_egdrift_bas654.gif

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 ec_egdrift_bas654.gif

(4) For further information on electrical characteristics of LVDS interface circuits, see the TIA-644-A standard and design note Interface Circuits for TIA/EIA-644 (LVDS).

7.10 Electrical Characteristics: AMC1304x25-Q1

All minimum and maximum specifications are at T_A = –40°C to 125°C, LDOIN = 4.0 V to 18.0 V, DVDD = 3.0 V to 5.5 V, AINP = –250 mV to 250 mV, AINN = 0 V, and sinc³ filter with OSR = 256, unless otherwise noted. Typical values are at T_A = 25°C, CLKIN = 20 MHz, LDOIN = 15.0 V, and DVDD = 3.3 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUTS
V_Clipping	Maximum differential voltage input range (AINP-AINN)			±312.5		mV
FSR	Specified linear full-scale range (AINP-AINN)		–250		250	mV
V_CM	Operating common-mode input range		–0.16		1.2	V
C_ID	Differential input capacitance			1		pF
I_IB	Input bias current	Inputs shorted to AGND	–82	–60	–48	μA
R_ID	Differential input resistance			25		kΩ
I_IO	Input offset current			±5		nA
CMTI	Common-mode transient immunity		15			kV/μs
CMRR	Common-mode rejection ratio	f_IN = 0 Hz, V_{CM min} ≤ V_IN ≤ V_{CM max}		–98		dB
CMRR	Common-mode rejection ratio	f_IN from 0.1 Hz to 50 kHz, V_{CM min} ≤ V_IN ≤ V_{CM max}		–98		dB
BW	Input bandwidth			1000		kHz
DC ACCURACY
DNL	Differential nonlinearity	Resolution: 16 bits	–0.99		0.99	LSB
INL	Integral nonlinearity⁽¹⁾	Resolution: 16 bits	–4	±1.5	4	LSB
E_O	Offset error	Initial, at 25°C	–100	±25	100	µV
TCE_O	Offset error thermal drift⁽²⁾		–1.3		1.3	μV/°C
E_G	Gain error	Initial, at 25°C	–0.2%	–0.05%	0.2%
TCE_G	Gain error thermal drift⁽³⁾		–40	±20	40	ppm/°C
PSRR	Power-supply rejection ratio	LDOIN from 4 V to 18 V, at dc		–110		dB
PSRR	Power-supply rejection ratio	LDOIN from 4 V to 18 V, from 0.1 Hz to 50 kHz		–110		dB
AC ACCURACY
SNR	Signal-to-noise ratio	f_IN = 1 kHz	82	85		dB
SINAD	Signal-to-noise + distortion	f_IN = 1 kHz	80	84		dB
THD	Total harmonic distortion	f_IN = 1 kHz		–90	–81	dB
SFDR	Spurious-free dynamic range	f_IN = 1 kHz	81	90		dB
DIGITAL INPUTS/OUTPUTS
External Clock
f_CLKIN	Input clock frequency		5	20	20.1	MHz
Duty_CLKIN	Duty cycle	5 MHz ≤ f_CLKIN ≤ 20.1 MHz	40%	50%	60%
CMOS Logic Family (AMC1304M25-Q1, CMOS with Schmitt Trigger)
I_IN	Input current	DGND ≤ V_IN ≤ DVDD	–1		1	μA
C_IN	Input capacitance			5		pF
V_IH	High-level input voltage		0.7 × DVDD		DVDD + 0.3	V
V_IL	Low-level input voltage		–0.3		0.3 × DVDD	V
C_LOAD	Output load capacitance	f_CLKIN = 20 MHz		30		pF
V_OH	High-level output voltage	I_OH = –20 µA	DVDD – 0.1			V
V_OH	High-level output voltage	I_OH = –4 mA	DVDD – 0.4			V
V_OL	Low-level output voltage	I_OL = 20 µA			0.1	V
V_OL	Low-level output voltage	I_OL = 4 mA			0.4	V
LVDS Logic Family (AMC1304L25-Q1)⁽⁴⁾
V_T	Differential output voltage	R_LOAD = 100 Ω	250	350	450	mV
V_OC	Common-mode output voltage		1.125	1.23	1.375	V
V_ID	Differential input voltage		100	350	600	mV
V_IC	Common-mode input voltage	V_ID = 100 mV	0.05	1.25	3.25	V
I_I	Receiver input current	DGND ≤ V_IN ≤ 3.3 V	–24	0	20	µA
POWER SUPPLY
LDOIN	LDOIN pin input voltage		4.0	15.0	18.0	V
VCAP	VCAP pin voltage			3.45		V
I_LDOIN	LDOIN pin input current			5.3	6.5	mA
DVDD	Controller-side supply voltage		3.0	3.3	5.5	V
I_DVDD	Controller-side supply current	LVDS, R_LOAD = 100 Ω		6.1	8.0	mA
		CMOS, 3.0 V ≤ DVDD ≤ 3.6 V, C_LOAD = 5 pF		2.7	4.0
		CMOS, 4.5 V ≤ DVDD ≤ 5.5 V, C_LOAD = 5 pF		3.2	5.5

(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.

(2) Offset error drift is calculated using the box method as described by the following equation:
AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 ec_eodrift_bas654.gif

(3) Gain error drift is calculated using the box method as described by the following equation:
AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 ec_egdrift_bas654.gif

(4) For further information on electrical characteristics of LVDS interface circuits, see the TIA-644-A standard and design note Interface Circuits for TIA/EIA-644 (LVDS).

7.11 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_CLK	CLKIN, CLKIN_N clock period		49.75	50	200	ns
t_HIGH	CLKIN, CLKIN_N clock high time		19.9	25	120	ns
t_LOW	CLKIN, CLKIN_N clock low time		19.9	25	120	ns
t_D	Falling edge of CLKIN, CLKIN_N to DOUT, DOUT_N valid delay		0		15	ns
t_ISTART	Interface startup time	DVDD at 3.0 V (min) to DOUT, DOUT_N valid with LDO_IN > 4 V	32		32	CLKIN cycles
t_ASTART	Analog startup time	LDOIN step to 4 V with DVDD ≥ 3.0 V, and 0.1 µF at VCAP pin		1		ms

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 tim_int_bas654.gif

Figure 1. Digital Interface Timing

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 tim_start_bas654.gif

Figure 2. Digital Interface Startup Timing

7.12 Insulation Characteristics Curves

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D043_SBAS655.gif

LDOIN = 18 V (worst case)

Figure 3. Thermal Derating Curve for Safety Limiting Current per VDE

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 Figure 3.gif

T_A up to 150°C, stress voltage frequency = 60 Hz

Figure 5. Reinforced Isolation Capacitor Lifetime Projection

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D044_SBAS655.gif

Figure 4. Thermal Derating Curve for Safety Limiting Power per VDE

7.13 Typical Characteristics

At LDOIN = 15.0 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1304x05-Q1) or –250 mV to 250 mV (AMC1304x25-Q1), AINN = 0 V, f_CLKIN = 20 MHz, and sinc³ filter with OSR = 256, unless otherwise noted.

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D001_SBAS799.gif

Figure 6. Input Current vs Input Common-Mode Voltage

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D003_SBAS655.gif

Figure 8. Integral Nonlinearity vs Input Signal Amplitude

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D005_SBAS655.gif

AMC1304x25-Q1

Figure 10. Offset Error vs LDO Input Supply Voltage

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D007_SBAS655.gif

AMC1304x25-Q1

Figure 12. Offset Error vs Temperature

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D009_SBAS799.gif

Figure 14. Offset Error vs Clock Frequency

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D011_SBAS654.gif

Figure 16. Gain Error vs Temperature

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D013_SBAS655.gif

Figure 18. Power-Supply Rejection Ratio vs
Ripple Frequency

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D015_SBAS799.gif

Figure 20. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs Temperature

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D017_SBAS799.gif

Figure 22. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs Input Signal Frequency

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D019_SBAS654.gif

AMC1304x05-Q1

Figure 24. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs Input Signal Amplitude

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D021_SBAS654.gif

Figure 26. Total Harmonic Distortion vs Temperature

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D023_SBAS654.gif

Figure 28. Total Harmonic Distortion vs
Input Signal Frequency

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D025_SBAS655.gif

AMC1304x05-Q1

Figure 30. Total Harmonic Distortion vs
Input Signal Amplitude

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D027_SBAS655.gif

Figure 32. Spurious-Free Dynamic Range vs Temperature

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D029_SBAS655.gif

Figure 34. Spurious-Free Dynamic Range vs
Input Signal Frequency

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D031_SBAS655.gif

AMC1304x05-Q1

Figure 36. Spurious-Free Dynamic Range vs
Input Signal Amplitude

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D033_SBAS655.gif

AMC1304x05-Q1, 4096-point FFT, V_IN = 100 mV_PP

Figure 38. Frequency Spectrum with 5-kHz Input Signal

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D035_SBAS655.gif

AMC1304x25-Q1, 4096-point FFT, V_IN = 500 mV_PP

Figure 40. Frequency Spectrum with 5-kHz Input Signal

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D037_SBAS655.gif

Figure 42. LDO Input Supply Current vs Temperature

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D039_SBAS655.gif

Figure 44. Controller-Side Supply Current vs
Controller-Side Supply Voltage (3.3 V, min)

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D041_SBAS655.gif

Figure 46. Controller-Side Supply Current vs Temperature

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D002_SBAS799.gif

Figure 7. Common-Mode Rejection Ratio vs
Input Signal Frequency

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D004_SBAS654.gif

Figure 9. Integral Nonlinearity vs Temperature

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D006_SBAS655.gif

AMC1304x05-Q1

Figure 11. Offset Error vs LDO Input Supply Voltage

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D008_SBAS654.gif

AMC1304x05-Q1

Figure 13. Offset Error vs Temperature

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D010_SBAS655.gif

Figure 15. Gain Error vs LDO Input Supply Voltage

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D012_SBAS654.gif

Figure 17. Gain Error vs Clock Frequency

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D014_SBAS799.gif

Figure 19. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs LDO Input Supply Voltage

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D016_SBAS799.gif

Figure 21. Signal-to-Noise Ratio and Signal-to-Noise + Distortion vs Clock Frequency

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D018_SBAS655.gif

AMC1304x25-Q1

Figure 23. SNR and SINAD vs Input Signal Amplitude

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D020_SBAS655.gif

Figure 25. Total Harmonic Distortion vs
LDO Input Supply Voltage

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D022_SBAS654.gif

Figure 27. Total Harmonic Distortion vs Clock Frequency

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D024_SBAS655.gif

AMC1304x25-Q1

Figure 29. Total Harmonic Distortion vs
Input Signal Amplitude

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D026_SBAS655.gif

Figure 31. Spurious-Free Dynamic Range vs
LDO Input Supply Voltage

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D028_SBAS655.gif

Figure 33. Spurious-Free Dynamic Range vs
Clock Frequency

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D030_SBAS655.gif

AMC1304x25-Q1

Figure 35. Spurious-Free Dynamic Range vs
Input Signal Amplitude

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D032_SBAS655.gif

AMC1304x05-Q1, 4096-point FFT, V_IN = 100 mV_PP

Figure 37. Frequency Spectrum with 1-kHz Input Signal

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D034_SBAS655.gif

AMC1304x25-Q1, 4096-point FFT, V_IN = 500 mV_PP

Figure 39. Frequency Spectrum with 1-kHz Input Signal

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D036_SBAS655.gif

Figure 41. LDO Input Supply Current vs
LDO Input Supply Voltage

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D038_SBAS655.gif

Figure 43. LDO Input Supply Current vs Clock Frequency

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D040_SBAS655.gif

Figure 45. Controller-Side Supply Current vs
Controller-Side Supply Voltage (5 V, min)

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 D042_SBAS655.gif

Figure 47. Controller-Side Supply Current vs
Clock Frequency

8 Detailed Description

8.1 Overview

The differential analog input (AINP and AINN) of the AMC1304-Q1 is a fully-differential amplifier feeding the switched-capacitor input of a second-order, delta-sigma (ΔΣ) modulator stage that digitizes the input signal into a 1-bit output stream. The isolated data output (DOUT and DOUT_N) of the converter provides a stream of digital ones and zeros that is synchronous to the externally-provided clock source at the CLKIN pin with a frequency in the range of 5 MHz to 20.1 MHz. The time average of this serial bit-stream output is proportional to the analog input voltage.

The Functional Block Diagram section shows a detailed block diagram of the AMC1304-Q1. The analog input range is tailored to directly accommodate a voltage drop across a shunt resistor used for current sensing. The SiO₂-based capacitive isolation barrier supports a high level of magnetic field immunity as described in the ISO72x Digital Isolator Magnetic-Field Immunity application report (SLLA181A), available for download at www.ti.com. The external clock input simplifies the synchronization of multiple current-sensing channels on the system level. The extended frequency range of up to 20 MHz supports higher performance levels compared to the other solutions available on the market.

8.2 Functional Block Diagram

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 ai_fbd_bas799.gif

8.3 Feature Description

8.3.1 Analog Input

The AMC1304-Q1 incorporates a front-end circuitry that contains a differential amplifier and sampling stage, followed by a ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors to a factor of 4 for devices with a specified input voltage range of ±250 mV (this value is for the AMC1304x25-Q1), or to a factor of 20 in devices with a ±50-mV input voltage range (for the AMC1304x05-Q1), resulting in a differential input impedance of 5 kΩ (for the AMC1304x05-Q1) or 25 kΩ (for the AMC1304x25-Q1).

Consider the input impedance of the AMC1304-Q1 in designs with high-impedance signal sources that can cause degradation of gain and offset specifications. The importance of this effect, however, depends on the desired system performance. Additionally, the input bias current caused by the internal common-mode voltage at the output of the differential amplifier causes an offset that is dependent on the actual amplitude of the input signal. See the Isolated Voltage Sensing section for more details on reducing these effects.

There are two restrictions on the analog input signals (AINP and AINN). First, if the input voltage exceeds the range AGND – 6 V to 3.7 V, the input current must be limited to 10 mA because the device input electrostatic discharge (ESD) diodes turn on. In addition, the linearity and noise performance of the device are ensured only when the differential analog input voltage remains within the specified linear full-scale range (FSR), that is ±250 mV (for the AMC1304x25-Q1) or ±50 mV (for the AMC1304x05-Q1), and within the specified input common-mode range.

8.3.2 Modulator

The modulator implemented in the AMC1304-Q1 is a second-order, switched-capacitor, feed-forward ΔΣ modulator, such as the one conceptualized in Figure 48. The analog input voltage V_IN and the output V₅ of the 1-bit digital-to-analog converter (DAC) are differentiated, providing an analog voltage V₁ at the input of the first integrator stage. The output of the first integrator feeds the input of the second integrator stage, resulting in output voltage V₃ that is differentiated with the input signal V_IN and the output of the first integrator V₂. Depending on the polarity of the resulting voltage V₄, the output of the comparator is changed. In this case, the 1-bit DAC responds on the next clock pulse by changing its analog output voltage V₅, causing the integrators to progress in the opposite direction and forcing the value of the integrator output to track the average value of the input.

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 ai_modulator_bas654.gif

Figure 48. Block Diagram of a Second-Order Modulator

The modulator shifts the quantization noise to high frequencies, as shown in Figure 49. Therefore, use a low-pass digital filter at the output of the device to increase the overall performance. This filter is also used to convert from the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's microcontroller families TMS320F2807x and TMS320F2837x offer a suitable programmable, hardwired filter structure termed a sigma-delta filter module (SDFM) optimized for usage with the AMC1304-Q1 family. Alternatively, a field-programmable gate array (FPGA) can be used to implement the digital filter.

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 ai_quant_noise_sbas655.gif

Figure 49. Quantization Noise Shaping

8.3.3 Digital Output

A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A differential input of 250 mV (for the AMC1304x25-Q1) or 50 mV (for the AMC1304x05-Q1) produces a stream of ones and zeros that are high 90% of the time. A differential input of –250 mV (–50 mV for the AMC1304x05-Q1) produces a stream of ones and zeros that are high 10% of the time. These input voltages are also the specified linear ranges of the different AMC1304-Q1 versions with performance as specified in this data sheet. If the input voltage value exceeds these ranges, the output of the modulator shows non-linear behavior when the quantization noise increases. The output of the modulator clips with a stream of only zeros with an input less than or equal to –312.5 mV (–62.5 mV for the AMC1304x05-Q1) or with a stream of only ones with an input greater than or equal to 312.5 mV (62.5 mV for the AMC1304x05-Q1). In this case, however, the AMC1304-Q1 generates a single 1 (if the input is at negative full-scale) or 0 every 128 clock cycles to indicate proper device function (see the Fail-Safe Output section for more details). The input voltage versus the output modulator signal is shown in Figure 50.

The density of ones in the output bit-stream for any input voltage value (with the exception of a full-scale input signal, as described in the Output Behavior in Case of a Full-Scale Input section) can be calculated using Equation 1:

Equation 1. AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 ai_equation1_bas654.gif

The AMC1304-Q1 system clock is typically 20 MHz and is provided externally at the CLKIN pin. Data are synchronously provided at 20 MHz at the DOUT pin. Data change at the CLKIN falling edge. For more details, see the Switching Characteristics table.

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 ai_anain-modout_bas512.gif

Figure 50. Analog Input versus AMC1304-Q1 Modulator Output

8.4 Device Functional Modes

8.4.1 Fail-Safe Output

In the case of a missing high-side supply voltage (LDOIN), the output of a ΔΣ modulator is not defined and can cause a system malfunction. In systems with high safety requirements, this behavior is not acceptable. Therefore, the AMC1304-Q1 implements a fail-safe output function that ensures the device maintains its output level in case of a missing LDOIN, as shown in Figure 51.

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 ai_failsafe_bas655.gif

Figure 51. Fail-Safe Output of the AMC1304-Q1

8.4.2 Output Behavior in Case of a Full-Scale Input

If a full-scale input signal is applied to the AMC1304-Q1 (that is, V_IN ≥ V_Clipping), the device generates a single one or zero every 128 bits at DOUT, depending on the actual polarity of the signal being sensed, as shown in Figure 52. In this way, differentiating between a missing LDOIN and a full-scale input signal is possible on the system level.

AMC1304L05-Q1 AMC1304L25-Q1 AMC1304M05-Q1 AMC1304M25-Q1 ai_FSinput_bas799.gif

Figure 52. Overrange Output of the AMC1304-Q1