The open-drain output powers up in a high-impedance (Hi-Z) state when the low-side supply (VDD2) turns on. After power-up, if the high-side is not functional yet, the output is actively pulled low. As shown in Figure 6-5, this condition happens after the low-side start-up time plus the high-side fault detection delay time (t_LS,STA + t_HS,FLT). Similarly, if the high-side supply drops below the undervoltage threshold (VDD1_UV), as described in Figure 6-8, for more than the high-side fault detection delay time during normal operation, the open-drain output is pulled low. This delay allows the system to shut down reliably when the high-side supply is missing.

Communication start between the high-side and low-side of the comparator is delayed by the high-side blanking time (t_HS,BLK, a time constant implemented on the high-voltage side) to allow the voltage on the REF pin to settle, and to avoid unintentional switching of the comparator output during power-up.

Figure 6-5 through Figure 6-10 depict typical power-up and power-down scenarios.

In Figure 6-5, the low-side supply (VDD2) turns on but the high-side supply (VDD1) remains off. The output powers up in a Hi-Z state. After t_{HS, FLT}, OUT is pulled low indicating a no-power fault on the high-side.

In Figure 6-6, the high-side supply (VDD1) turns on long after the low-side supply (VDD2) turns on. The output is initially in an active-low state, see Figure 6-5. After the high-side supply is enabled, there is a duration of t_{HS, STA} + t_{HS, BLK} before the device assumes normal operation and the output reflects the current state of the comparator.

Figure 6-5 VDD2 Turns On, VDD1 Stays Off

Figure 6-6 VDD2 is On; VDD1 Turns On
(Long Delay)

In Figure 6-7, the low-side supply (VDD2) turns on, followed by the high-side supply (VDD1) with only a short delay. The output is initially in a Hi-Z state. The high-side fault detection delay (t_HS,FLT) is shorter than the high-side blanking time (t_HS,BLK), and therefore the output is pulled low after t_HS,FLT, indicating that the high-side is not operational yet. After the high-side blanking time (t_HS,BLK) elapses, the device assumes normal operation and the output reflects the current state of the comparator.

In Figure 6-8, the high-side supply (VDD1) turns off, followed by the low-side supply (VDD2). After the high-side fault detection delay time (t_HS,FLT), the output is actively pulled low. As soon as VDD2 drops below the VDD2_UV threshold, the output enters a Hi-Z state.

Figure 6-7 VDD2 Turns On, Followed by VDD1
(Short Delay)

Figure 6-8 VDD1 Turns Off, Followed by VDD2

In Figure 6-9, the low-side supply (VDD2) turns on after the high-side is fully powered up (the delay between VDD1 and VDD2 is greater than (t_HS,STA + t_HS,BLK)). The output starts in a Hi-Z state. After the low-side start-up time (t_LS,STA), the device enters normal operation.

In Figure 6-10, the low-side supply (VDD2) turns off, followed by the high-side supply (VDD1). As soon as VDD2 drops below the VDD2_UV threshold, the output enters a Hi-Z state.

Figure 6-9 VDD1 Turns On, Followed by VDD2
(Long Delay)

Figure 6-10 VDD2 Turns Off, Followed by VDD1