SBASAW1A September 2023 – December 2023 AMC21C12
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
LATCH INPUT | ||||||
Deglitch time | Falling edge | 1.8 | 3.2 | µs | ||
OPEN-DRAIN OUTPUT | ||||||
tpH | Propagation delay time, |VIN| rising | VDD2 = 3.3 V, VREF = 250 mV, VOVERDRIVE = 10 mV, CL = 15 pF |
280 | 410 | ns | |
VDD2 = 3.3 V, VREF = 2 V, VOVERDRIVE = 50 mV, CL = 15 pF |
240 | 370 | ||||
tpL | Propagation delay time, |VIN| falling | VDD2 = 3.3 V, VREF = 250 mV, VOVERDRIVE = 10 mV, CL = 15 pF |
280 | 410 | ns | |
VDD2 = 3.3 V, VREF = 2 V, VOVERDRIVE = 50 mV, CL = 15 pF |
240 | 370 | ||||
tf | Output signal fall time | RPULLUP = 4.7 kΩ, CL = 15 pF | 2 | ns | ||
MODE SELECTION | ||||||
tHSEL | Comparator hysteresis selection deglitch time | Cmp0, VREF rising or falling | 10 | µs | ||
tDIS13 | Comparator disable deglitch time | Cmp1, VREF rising | 10 | µs | ||
tEN13 | Comparator enable deglitch time | Cmp1, VREF falling | 100 | µs | ||
START-UP TIMING | ||||||
tLS,STA | Low-side start-up time | VDD2 step to 2.7 V, VDD1 ≥ 3.0 V | 40 | µs | ||
tHS,STA | High-side start-up time | VDD1 step to 3.0 V, VDD2 ≥ 2.7 V | 45 | µs | ||
tHS,BLK | High-side blanking time | 200 | µs | |||
tHS,FLT | High-side-fault detection delay time | 100 | µs |