SBASAC9A February   2022  – July 2022 AMC23C11

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information 
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications 
    8. 6.8  Safety Limiting Values 
    9. 6.9  Electrical Characteristics 
    10. 6.10 Switching Characteristics 
    11. 6.11 Timing Diagrams
    12. 6.12 Insulation Characteristics Curves
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Reference Input
      3. 7.3.3 Isolation Channel Signal Transmission
      4. 7.3.4 Open-Drain Digital Output
        1. 7.3.4.1 Transparent Output Mode
        2. 7.3.4.2 Latch Output Mode
      5. 7.3.5 Power-Up and Power-Down Behavior
      6. 7.3.6 VDD1 Brownout and Power-Loss Behavior
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 DC Link Overcurrent Detection
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
    3. 8.3 Application Curves
    4. 8.4 Best Design Practices
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5 Power-Up and Power-Down Behavior

The open-drain output powers up in a high-impedance (Hi-Z) state when the low-side supply (VDD2) turns on. After power-up, if the high-side is not functional yet, the output is actively pulled low. This condition happens after the low-side start-up time plus the high-side fault detection delay time (tLS,STA + tHS,FLT), as shown in Figure 7-5. Similarly, if the high-side supply drops below its undervoltage threshold (VDD1UV) for more than the high-side fault detection delay time during normal operation, the open-drain output is pulled low, as shown in Figure 7-8. This delay allows the system to shut down reliably when the high-side supply is missing.

Communication starts between the high-side and low-side of the comparator is delayed by the high-side blanking time (tHS,BLK, a time constant implemented on the high-voltage side) to allow the internal 300-mV reference and the voltage on the REF pin to settle, and to avoid unintentional switching of the comparator output during power-up.

Figure 7-5 through Figure 7-10 depict typical power-up and power-down scenarios.

In Figure 7-5, the low-side supply (VDD2) turns on but the high-side supply (VDD1) remains off. The output powers up in a Hi-Z state. After tHS, FLT, OUT is pulled low indicating a no-power fault on the high-side.

In Figure 7-6, the high-side supply (VDD1) turns on long after the low-side supply (VDD2) turns on. The output is initially in an active-low state, see case (1). After the high-side supply is enabled, there is a duration of tHS, STA + tHS, BLK before the device assumes normal operation and the output reflects the current state of the comparator.

Figure 7-5 VDD2 Turns On, VDD1 Stays Off
Figure 7-6 VDD2 is On; VDD1 Turns On
(Long Delay)

In Figure 7-7, the low-side supply (VDD2) turns on, followed by the high-side supply (VDD1) with only a short delay. The output is initially in a Hi-Z state. The high-side fault detection delay (tHS,FLT) is shorter than the high-side blanking time (tHS,BLK), and therefore the output is pulled low after tHS,FLT, indicating that the high-side is not operational yet. After the high-side blanking time (tHS,BLK) elapses, the device assumes normal operation and the output reflects the current state of the comparator.

In Figure 7-8, the high-side supply (VDD1) turns off, followed by the low-side supply (VDD2). After the high-side fault detection delay time (tHS,FLT), the output is actively pulled low. As soon as VDD2 drops below the VDD2UV threshold, the output enters a Hi-Z state.

Figure 7-7 VDD2 Turns On, Followed by VDD1
(Short Delay)
Figure 7-8 VDD1 Turns Off, Followed by VDD2

In Figure 7-9, the low-side supply (VDD2) turns on after the high-side is fully powered up (the delay between VDD1 and VDD2 is greater than (tHS,STA + tHS,BLK)). After the low-side start-up time (tLS,STA), the device enters normal operation.

In Figure 7-10, the low-side supply (VDD2) turns off, followed by the high-side supply (VDD1). As soon as VDD2 drops below the VDD2UV threshold, the output enters a Hi-Z state.

Figure 7-9 VDD1 Turns On, Followed by VDD2
(Long Delay)
Figure 7-10 VDD2 Turns Off, Followed by VDD1