SBASAC9A February   2022  – July 2022 AMC23C11

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information 
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications 
    8. 6.8  Safety Limiting Values 
    9. 6.9  Electrical Characteristics 
    10. 6.10 Switching Characteristics 
    11. 6.11 Timing Diagrams
    12. 6.12 Insulation Characteristics Curves
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Reference Input
      3. 7.3.3 Isolation Channel Signal Transmission
      4. 7.3.4 Open-Drain Digital Output
        1. 7.3.4.1 Transparent Output Mode
        2. 7.3.4.2 Latch Output Mode
      5. 7.3.5 Power-Up and Power-Down Behavior
      6. 7.3.6 VDD1 Brownout and Power-Loss Behavior
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 DC Link Overcurrent Detection
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
    3. 8.3 Application Curves
    4. 8.4 Best Design Practices
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.4.2 Latch Output Mode

Some applications do not have the functionality available to continuously monitor the state of the OUT pin to detect an overcurrent condition. A typical example of this application is a system that is only able to poll the OUT terminal state periodically to determine if the system is functioning correctly. If the device is set to transparent mode in this type of application, a change in the state of the OUT pin can be missed if the out-of-range condition does not appear during one of these periodic polling events.

Latch mode is specifically intended to accommodate these applications. The device is placed in latch mode by setting the voltage on the LATCH terminal to a logic high level. The difference between latch mode and transparent mode is how the output responds when an out-of-range event ends. In transparent mode, when the input signal drops below the trip threshold, the output state returns to the default high setting to indicate that the out-of-range event has ended.

In latch mode, when an out-of-range condition is detected and the OUT pin is pulled low, the OUT pin does not return to the default high level when the input signal drops below the trip threshold level. To clear the event, the LATCH terminal must be pulled low for at least 4 μs. Pulling the LATCH pin low allows the OUT pin to return to the default high level, provided that the input signal has dropped below the trip threshold. If the input signal is still above the threshold when the LATCH pin is pulled low, the OUT terminal remains low. When the out-of-range event is detected by the system controller, the LATCH pin can be set back to high in order to place the device back into latch mode.