SWRS248D April   2020  – January 2022 AWR6443 , AWR6843

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
    1.     Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
      1. 6.2.1 Signal Descriptions - Digital
      2. 6.2.2 Signal Descriptions - Analog
    3. 6.3 Pin Attributes
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Supply Specifications
    6. 7.6  Power Consumption Summary
    7. 7.7  RF Specification
    8. 7.8  CPU Specifications
    9. 7.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1  Power Supply Sequencing and Reset Timing
      2. 7.10.2  Input Clocks and Oscillators
        1. 7.10.2.1 Clock Specifications
      3. 7.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.10.3.1 Peripheral Description
        2. 7.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. 7.10.3.2.1 SPI Timing Conditions
          2. 7.10.3.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. 7.10.3.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 7.10.3.3 SPI Peripheral Mode I/O Timings
          1. 7.10.3.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (1) (1)
        4. 7.10.3.4 Typical Interface Protocol Diagram (Peripheral Mode)
      4. 7.10.4  LVDS Interface Configuration
        1. 7.10.4.1 LVDS Interface Timings
      5. 7.10.5  General-Purpose Input/Output
        1. 7.10.5.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      6. 7.10.6  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.10.6.1 Dynamic Characteristics for the CANx TX and RX Pins
      7. 7.10.7  Serial Communication Interface (SCI)
        1. 7.10.7.1 SCI Timing Requirements
      8. 7.10.8  Inter-Integrated Circuit Interface (I2C)
        1. 7.10.8.1 I2C Timing Requirements
      9. 7.10.9  Quad Serial Peripheral Interface (QSPI)
        1. 7.10.9.1 QSPI Timing Conditions
        2. 7.10.9.2 Timing Requirements for QSPI Input (Read) Timings
        3. 7.10.9.3 QSPI Switching Characteristics
      10. 7.10.10 ETM Trace Interface
        1. 7.10.10.1 ETMTRACE Timing Conditions
        2. 7.10.10.2 ETM TRACE Switching Characteristics
      11. 7.10.11 Data Modification Module (DMM)
        1. 7.10.11.1 DMM Timing Requirements
      12. 7.10.12 JTAG Interface
        1. 7.10.12.1 JTAG Timing Conditions
        2. 7.10.12.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 7.10.12.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
      2. 8.3.2 Processor Subsystem
      3. 8.3.3 Automotive Interface
      4. 8.3.4 Host Interface
      5. 8.3.5 Main Subsystem Cortex-R4F
      6. 8.3.6 DSP Subsystem
      7. 8.3.7 Hardware Accelerator
    4. 8.4 Other Subsystems
      1. 8.4.1 ADC Channels (Service) for User Application
        1. 8.4.1.1 GP-ADC Parameter
  9. 9 Monitoring and Diagnostics
    1. 9.1 Monitoring and Diagnostic Mechanisms
      1. 9.1.1 Error Signaling Module
  10. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Reference Schematic
  11. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information
    2. 12.2 Tray Information for ABL, 10.4 × 10.4 mm

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABL|161
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Device Comparison

Unless otherwise noted, the device-specific information, in this document, relates to both the AWR6843 and AWR6443 devices. The device differences are highlighted in Table 5-1, Device Features Comparison.

Table 5-1 Device Features Comparison
FUNCTION AWR6843AOP AWR1843AOP AWR6843(1) AWR6443(1) AWR1843 AWR1642 AWR1443
Antenna on Package (AOP) Yes Yes — — — — —
Number of receivers 4 4 4 4 4 4 4
Number of transmitters 3(2) 3(2) 3(2) 3(2) 3(2) 2 3
RF frequency range 60 to 64 GHz 76 to 81 GHz 60 to 64 GHz 60 to 64 GHz 76 to 81 GHz 76 to 81 GHz 76 to 81 GHz
On-chip memory 1.75MB 2MB 1.75MB 1.4MB 2MB 1.5MB 576KB
Max I/F (Intermediate Frequency) (MHz) 10 10 10 10 10 5 5
Max real sampling rate (Msps) 25 25 25 25 25 12.5 12.5
Max complex sampling rate (Msps) 12.5 12.5 12.5 12.5 12.5 6.25 6.25
Device Security(3) Yes Yes Yes — Yes Yes —
Processors
MCU (R4F) Yes Yes Yes Yes Yes Yes Yes
DSP (C674x) Yes Yes Yes — Yes Yes —
Peripherals
Serial Peripheral Interface (SPI) ports 2 2 2 2 2 2 1
Quad Serial Peripheral Interface (QSPI) Yes Yes Yes Yes Yes Yes Yes
Inter-Integrated Circuit (I2C) interface 1 1 1 1 1 1 1
Controller Area Network (DCAN) interface — 1 — — 1 1 1
Controller Area Network (CAN-FD) interface 2 1 2 2 1 — —
Trace Yes Yes Yes Yes Yes Yes —
PWM Yes Yes Yes Yes Yes Yes —
Hardware In Loop (HIL/DMM) Yes Yes Yes Yes Yes Yes —
GPADC Yes Yes Yes Yes Yes Yes Yes
LVDS/Debug(4) Yes Yes Yes Yes Yes Yes Yes
CSI2 — — — — — — —
Hardware accelerator Yes Yes Yes Yes Yes — Yes
1-V bypass mode Yes Yes Yes Yes Yes Yes Yes
JTAG Yes Yes Yes Yes Yes Yes Yes
Product status Product Preview (PP),
Advance Information (AI),
or Production Data (PD)		 PD(5) PD(5) PD(5) PD(5) PD(5) PD(5) PD(5)
(1) Developed for Functional Safety applications, the device supports hardware integrity upto ASIL-B. Refer to the related documentation for more details. Non-Functional Safety Variants are also available for AWR6843 device.
(2) 3 Tx Simultaneous operation is supported only with 1-V LDO bypass and PA LDO disable mode. In this mode, the 1-V supply needs to be fed on the VOUT PA pin.
(3) Device security features including Secure Boot and Customer Programmable Keys are available in select devices for only select part variants as indicated by the Device Type identifier in Section 3, Device Information table.
(4) The LVDS interface is not a production interface and is only used for debug.
(5) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. ADVANCE INFORMATION for pre-production products; subject to change without notice.