SLUSAO0H November 2011 – July 2022 BQ24160 , BQ24160A , BQ24161 , BQ24161B , BQ24163 , BQ24168
PRODUCTION DATA
Memory location: 02, Reset state: 1000 1100
BIT | NAME | READ/WRITE | FUNCTION |
---|---|---|---|
B7 (MSB) | RESET | Write only | Write: 1 – Reset all registers to default values 0 – No effect Read: always get 1 |
B6 | IUSB_LIMIT_2 | Read/Write | 000 – USB2.0 host with 100-mA current limit 001 – USB3.0 host with 150-mA current limit 010 – USB2.0 host with 500-mA current limit 011 – USB host/charger with 800-mA current limit 100 – USB3.0 host with 900-mA current limit 101 – USB host/charger with 1500-mA current limit 110–111 – NA (default 000(1)) |
B5 | IUSB_LIMIT_1 | Read/Write | |
B4 | IUSB_LIMIT _0 | Read/Write | |
B3 | EN_STAT | Read/Write | 1 – Enable STAT output to show charge status, 0-Disable STAT output for charge status. Fault interrupts are still show even when EN_STAT = 0. (default 1) |
B2 | TE | Read/Write | 1 – Enable charge current termination, 0-Disable charge current termination (default 1) |
B1 | CE | Read/Write | 1 – Charging is disabled 0 – Charging enabled (default 0 BQ24160/1/1B/3/8) |
B0 (LSB) | HZ_MODE | Read/Write | 1 – High impedance mode 0 – Not high impedance mode (default 0) |
RESET Bit | |
The RESET bit in the control register (0x02h) is used to reset all the charge parameters. Write 1 to RESET bit to reset all the registers to default values and place the BQ2416xx into DEFAULT mode and turn off the watchdog timer. The RESET bit is automatically cleared to zero once the BQ2416xx enters DEFAULT mode. | |
CE Bit (Charge Enable) | |
The CE bit in the control register (0x02h) is used to disable or enable the charge process. A low logic level (0) on this bit enables the charge and a high logic level (1) disables the charge. When charge is disabled, the SYS output regulates to VSYS(REG) and battery is disconnected from the SYS. Supplement mode is still available if the system load demands cannot be met by the supply. | |
HZ_MODE Bit (High Impedance Mode Enable) | |
The HZ_MODE bit in the control register (0x02h) is used to disable or enable the high impedance mode. A low logic level (0) on this bit enables the IC and a high logic level (1) puts the IC in a low quiescent current state called high impedance mode. When in high impedance mode, the converter is off and the battery FET and BGATE are on. The load on SYS is supplied by the battery. |