SLUSAO0H November   2011  – July 2022 BQ24160 , BQ24160A , BQ24161 , BQ24161B , BQ24163 , BQ24168

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Charge Mode Operation
        1. 8.3.1.1 Charge Profile
        2. 8.3.1.2 PWM Controller in Charge Mode
      2. 8.3.2  Battery Charging Process
      3. 8.3.3  Battery Detection
      4. 8.3.4  Dynamic Power Path Management (DPPM)
      5. 8.3.5  Input Source Connected
      6. 8.3.6  Battery Only Connected
      7. 8.3.7  Battery Discharge FET (BGATE)
      8. 8.3.8  DEFAULT Mode
      9. 8.3.9  Safety Timer and Watchdog Timer (BQ24160/BQ24161/BQ24161B/BQ24163 only)
      10. 8.3.10 D+, D– Based Adapter Detection for the USB Input (D+, D–, BQ24160/0A/3)
      11. 8.3.11 USB Input Current Limit Selector Input (PSEL, BQ24161/161B/168 only)
      12. 8.3.12 Hardware Chip Disable Input (CD)
      13. 8.3.13 LDO Output (DRV)
      14. 8.3.14 External NTC Monitoring (TS)
      15. 8.3.15 Thermal Regulation and Protection
      16. 8.3.16 Input Voltage Protection in Charge Mode
        1. 8.3.16.1 Sleep Mode
        2. 8.3.16.2 Input Voltage Based DPM
        3. 8.3.16.3 Bad Source Detection
        4. 8.3.16.4 Input Overvoltage Protection
        5. 8.3.16.5 Reverse Boost (Boost Back) Prevention Circuit
      17. 8.3.17 Charge Status Outputs (STAT, INT)
      18. 8.3.18 Good Battery Monitor
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Description
        1. 8.5.1.1 F/S Mode Protocol
    6. 8.6 Register Maps
      1. 8.6.1 Status/Control Register (READ/WRITE)
      2. 8.6.2 Battery/ Supply Status Register (READ/WRITE)
      3. 8.6.3 Control Register (READ/WRITE)
      4. 8.6.4 Control/Battery Voltage Register (READ/WRITE)
      5. 8.6.5 Vender/Part/Revision Register (READ only)
      6. 8.6.6 Battery Termination/Fast Charge Current Register (READ/WRITE)
      7. 8.6.7 VIN-DPM Voltage/ DPPM Status Register
      8. 8.6.8 Safety Timer/ NTC Monitor Register (READ/WRITE)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Inductor and Capacitor Selection Guidelines
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Requirements for SYS Output
    2. 10.2 Requirements for Charging
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
      1.      Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.17 Charge Status Outputs (STAT, INT)

The STAT output is used to indicate operation conditions for BQ2416xx. STAT is pulled low during charging when EN_STAT bit in the control register (0x02h) is set to “1”. When charge is complete or disabled, STAT is high impedance. When a fault occurs, a 128-µs pulse (interrupt) is sent out to notify the host. The status of STAT during different operation conditions is summarized in Table 8-1. STAT drives an LED for visual indication or can be connected to the logic rail for host communication. The EN_STAT bit in the control register (00H) is used to enable/disable the charge status for STAT. The interrupt pulses are unaffected by EN_STAT and will always be shown. The INT output is identical to STAT and is used to interface with a low voltage host processor.

Table 8-1 STAT Pin Summary
CHARGE STATESTAT AND INT BEHAVIOR
Charge in progress and EN_STAT=1Low
Other normal conditionsHigh-Impedance
Status Changes: Supply Status Change (plug in or removal), safety timer fault, watchdog expiration, sleep mode, battery temperature fault (TS), battery fault (OVP or absent), thermal shutdown128-µs pulse, then High Impedance