SLUSBY5G June   2014  – December 2015

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1  High Impedance Mode
      2. 7.4.2  Battery Only Connected
      3. 7.4.3  Input Connected
        1. 7.4.3.1 Input Voltage Protection in Charge Mode
          1. 7.4.3.1.1 Sleep Mode
          2. 7.4.3.1.2 Input Voltage Based Dynamic Power Management (VIN-DPM)
          3. 7.4.3.1.3 Input Overvoltage Protection
        2. 7.4.3.2 Charge Profile
      4. 7.4.4  Battery Charging Process
      5. 7.4.5  Charge Time Optimizer
      6. 7.4.6  Battery Detection
      7. 7.4.7  Battery Overvoltage Protection (BOVP)
      8. 7.4.8  Dynamic Power Path Management
      9. 7.4.9  Battery Discharge FET (BGATE)
      10. 7.4.10 IUSB1, IUSB2, and IUSB3 Input
      11. 7.4.11 Safety Timer in Charge Mode
      12. 7.4.12 LDO Output (DRV)
      13. 7.4.13 External NTC Monitoring (TS)
      14. 7.4.14 Thermal Regulation and Protection
      15. 7.4.15 Status Outputs (CHG, PG)
      16. 7.4.16 Boost Mode Operation
        1. 7.4.16.1 PWM Controller in Boost Mode
        2. 7.4.16.2 Burst Mode during Light Load
        3. 7.4.16.3 CHG and PG During Boost Mode
        4. 7.4.16.4 Protection in Boost Mode
          1. 7.4.16.4.1 Output Over-Voltage Protection
          2. 7.4.16.4.2 Output Over-Current Protection
          3. 7.4.16.4.3 Battery Voltage Protection
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application, External Discharge FET
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Output Inductor and Capacitor Selection Guidelines
      2. 8.2.2 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Requirements for SYS Output
    2. 9.2 Requirements for Charging
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from F Revision (August 2015) to G Revision

  • Changed absolute maximum value for SYS, TS and I/O pins from 5.0 V to 5.5 V. Go
  • Added VIN > VUVLO test condition for VBATUVLO.Go
  • Changed image object for Figure 26 Go

Changes from E Revision (December 2014) to F Revision

  • Deleted devices bq24265 and bq24267 Go
  • Changed bq2426x To: bq24266 throughout the datasheet Go
  • Deleted Features: Host-controlled JEITA Compatible NTC Monitoring Input (bq24265)Go
  • Deleted Features: Voltage-based, JEITA Compatible NTC Monitoring Input (bq24266)Go
  • Changed text in the Description From: "The bq24265, bq24266, and bq24267 are.." To: "The bq24266 is.."Go
  • Changed 1µF to 2.2µF on the DRV pin of the Application SchematicGo
  • Deleted the Device Comparison TableGo
  • Deleted the bq24265 pinout imageGo
  • Changed the DRV pin description From: "1μF of ceramic capacitance" To: "a 2.2uF, 10V, X5R or better capacitor" in the Pin Functions tableGo
  • Changed absolute maximum value for DRV pin from 5.0 V to 5.5 V. Go
  • Moved the Stroage temperature to Absolute Maximum Ratings Go
  • Changed the Handling Ratings table To: ESD Ratings tableGo
  • Deleted references to BQ24265 and BQ24266 in VBATREG of the Electrical Characteristics Go
  • Deleted references to BQ24265 and BQ24266 in KISET of the Electrical Characteristics Go
  • Deleted text from the Overview section: "The bq24265 allows a host to monitor a NTC thermistor and adjust the charge current and voltage using the CE1 and CE2 pins." and "The bq24267 features a TS input with HOT/COLD support only."Go
  • Deleted text from the Charge Profile section: "using CE1 and CE2 (bq24265) or CE (bq24266/7)." Go
  • Deleted text from the Safety Timer in Charge Mode section: " (bq24266/7) and when CE1 and CE2 (bq24265) are configured according to Table 2.Go
  • Changed the External NTC Monitoring (CE1, CE2, and TS) section To: External NTC Monitoring (TS) Go
  • Deleted Table "CE1, CE2 Configurations"Go
  • Deleted text from the Application Information section: "but can be used to evaluate the bq24265 or bq24267 as well. To configure the board to use the bq24265, the /CE1 and /CE2 pins are used to comply with JEITA per Table 2. Go
  • Deleted the bq24265 Typical Application No External Discharge FET image Go

Changes from D Revision (October 2014) to E Revision

  • Changed "Select 100kΩ for the bottom resistor" to "Select 10kΩ for the bottom resistor" in the Input Voltage Based Dynamic Power Management (VIN-DPM) section.Go

Changes from C Revision (October 2014) to D Revision

  • Deleted text "TS faults are reported by the I2C interface"; bq24266/7 TS pin description. Go
  • Deleted text "or 2A (depending on the I2C setting)" from PWM Controller in Boost Mode description. Go

Changes from B Revision (September 2014) to C Revision

  • Changed the Test Conditions of VSYSREG(LO) From: VBAT < VMINSYS To: BAT < VMINSYS, battery attachedGo
  • Deleted list item 3: CE pin = high from Battery Discharge FET (BGATE) Go

Changes from A Revision (August 2014) to B Revision

Changes from * Revision (June 2014) to A Revision

  • Removed the Product Preview banner. Go