SLUS893B March 2010 – June 2015
PRODUCTION DATA.
PIN | DESCRIPTION | |
---|---|---|
NAME | NO. | |
BTST | 16 | PWM high-side driver negative supply. Connect the 0.1-μF bootstrap capacitor from PH to BTST, and a bootstrap Schottky diode from REGN to BTST. |
CE | 2 | Charge enable active-HIGH logic input. HI enables charge. LO disables charge. The CE pin has an internal 1-MΩ pulldown resistor. |
GND | 11 | Low-current sensitive analog/digital ground. On PCB layout, connect with thermal pad underneath the IC. |
HIDRV | 15 | PWM high-side driver output. Connect to the gate of the high-side power MOSFET with a short trace. |
ISET | 7 | Charge current set input. The voltage of ISET pin programs the charge current regulation, precharge current and termination current set-point. |
LODRV | 13 | PWM low-side driver output. Connect to the gate of the low-side power MOSFET with a short trace. |
PG | 5 | Open-drain power good status output. The transistor turns on when a valid VCC is detected. The transistor is turned off in the sleep mode. PG can be used to drive an LED or communicate with a host processor. The PG pin can be used to drive ACFET and BATFET. |
PH | 14 | PWM high-side driver negative supply. Connect to the phase-switching node (junction of the low-side power MOSFET drain, high-side power MOSFET source, and output inductor). |
REGN | 12 | PWM low-side driver positive 6-V supply output. Connect a 1-μF ceramic capacitor from REGN to the PGND pin, close to the IC. Use for low-side driver and high-side driver bootstrap voltage by connecting a small-signal Schottky diode from REGN to BTST. |
SRN | 9 | Charge current sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the SRN pin to GND for common-mode filtering. |
SRP | 10 | Charge current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from SRP pin to GND for common-mode filtering. |
STAT | 3 | Open-drain charge status pin to indicate various charger operations (See Table 2) |
Thermal pad | — | Exposed pad beneath the IC. Always solder the thermal pad to the board, and have vias on the thermal-pad plane star-connecting to GND and ground plane for high-current power converter. It also serves as a thermal pad to dissipate the heat. |
TS | 4 | Temperature qualification voltage input for battery pack negative-temperature-coefficient thermistor. Program the hot and cold temperature window with a resistor divider from VREF to TS to GND. |
VCC | 1 | IC power positive supply. Connect through a 10-Ω resistor to the common-source (diode-OR) point: source of high-side P-channel MOSFET and source of reverse-blocking power P-channel MOSFET. Or connect through a 10-Ω resistor to the cathode of the input diode. Place a 1-μF ceramic capacitor from VCC to GND pin close to the IC. |
VFB | 8 | Output voltage analog feedback adjustment. Connect the output of a resistive voltage divider from the battery terminals to this node to adjust the output battery regulation voltage. |
VREF | 6 | 3.3-V regulated voltage output. Place a 1-μF ceramic capacitor from VREF to the GND pin close to the IC. This voltage could be used for programming of voltage and current regulation and for programming the TS threshold. |