SLUSDO1B june 2019 – august 2023 BQ25155
PRODUCTION DATA
Table 9-8 lists the memory-mapped registers for the I2C registers. All register offset addresses not listed in Table 9-8 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Register Name | Section |
---|---|---|---|
0x0 | STAT0 | Charger Status 0 | Go |
0x1 | STAT1 | Charger Status 1 | Go |
0x2 | STAT2 | ADC Status | Go |
0x3 | FLAG0 | Charger Flags 0 | Go |
0x4 | FLAG1 | Charger Flags 1 | Go |
0x5 | FLAG2 | ADC Flags | Go |
0x6 | FLAG3 | Timer Flags | Go |
0x7 | MASK0 | Interrupt Masks 0 | Go |
0x8 | MASK1 | Interrupt Masks 1 | Go |
0x9 | MASK2 | Interrupt Masks 2 | Go |
0xA | MASK3 | Interrupt Masks 3 | Go |
0x12 | VBAT_CTRL | Battery Voltage Control | Go |
0x13 | ICHG_CTRL | Fast Charge Current Control | Go |
0x14 | PCHRGCTRL | Pre-Charge Current Control | Go |
0x15 | TERMCTRL | Termination Current Control | Go |
0x16 | BUVLO | Battery UVLO and Current Limit Control | Go |
0x17 | CHARGERCTRL0 | Charger Control 0 | Go |
0x18 | CHARGERCTRL1 | Charger Control 1 | Go |
0x19 | ILIMCTRL | Input Corrent Limit Control | Go |
0x1D | LDOCTRL | LDO Control | Go |
0x30 | MRCTRL | MR Control | Go |
0x35 | ICCTRL0 | IC Control 0 | Go |
0x36 | ICCTRL1 | IC Control 1 | Go |
0x37 | ICCTRL2 | IC Control 2 | Go |
0x40 | ADCCTRL0 | ADC Control 0 | Go |
0x41 | ADCCTRL1 | ADC Control 1 | Go |
0x42 | ADC_DATA_VBAT_M | ADC VBAT Measurement MSB | Go |
0x43 | ADC_DATA_VBAT_L | ADC VBAT Measurement LSB | Go |
0x44 | ADC_DATA_TS_M | ADC TS Measurement MSB | Go |
0x45 | ADC_DATA_TS_L | ADC TS Measurement LSB | Go |
0x46 | ADC_DATA_ICHG_M | ADC ICHG Measurement MSB | Go |
0x47 | ADC_DATA_ICHG_L | ADC ICHG Measurement LSB | Go |
0x48 | ADC_DATA_ADCIN_M | ADC ADCIN Measurement MSB | Go |
0x49 | ADC_DATA_ADCIN_L | ADC ADCIN Measurement LSB | Go |
0x4A | ADC_DATA_VIN_M | ADC VIN Measurement MSB | Go |
0x4B | ADC_DATA_VIN_L | ADC VIN Measurement LSB | Go |
0x4C | ADC_DATA_PMID_M | ADC VPMID Measurement MSB | Go |
0x4D | ADC_DATA_PMID_L | ADC VPMID Measurement LSB | Go |
0x4E | ADC_DATA_IIN_M | ADC IIN Measurement MSB | Go |
0x4F | ADC_DATA_IIN_L | ADC IIN Measurement LSB | Go |
0x52 | ADCALARM_COMP1_M | ADC Comparator 1 Threshold MSB | Go |
0x53 | ADCALARM_COMP1_L | ADC Comparator 1 Threshold LSB | Go |
0x54 | ADCALARM_COMP2_M | ADC Comparator 2 Threshold MSB | Go |
0x55 | ADCALARM_COMP2_L | ADC Comparator 2 Threshold LSB | Go |
0x56 | ADCALARM_COMP3_M | ADC Comparator 3 Threshold MSB | Go |
0x57 | ADCALARM_COMP3_L | ADC Comparator 3 Threshold LSB | Go |
0x58 | ADC_READ_EN | ADC Channel Enable | Go |
0x61 | TS_FASTCHGCTRL | TS Charge Control | Go |
0x62 | TS_COLD | TS Cold Threshold | Go |
0x63 | TS_COOL | TS Cool Threshold | Go |
0x64 | TS_WARM | TS Warm Threshold | Go |
0x65 | TS_HOT | TS Hot Threshold | Go |
0x6F | DEVICE_ID | Device ID | Go |
Complex bit access types are encoded to fit into small table cells. Table 9-9 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
RC | C R | to Clear Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
STAT0 is shown in Figure 9-16 and described in Table 9-10.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CHRG_CV_STAT | CHARGE_DONE_STAT | IINLIM_ACTIVE_STAT | VDPPM_ACTIVE_STAT | VINDPM_ACTIVE_STAT | THERMREG_ACTIVE_STAT | VIN_PGOOD_STAT |
R-X | R-X | R-X | R-X | R-X | R-X | R-X | R-X |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | X | Reserved |
6 | CHRG_CV_STAT | R | X | Constant Voltage Charging Mode (Taper Mode) Status
1b0 = Not Active 1b1 = Active |
5 | CHARGE_DONE_STAT | R | X | Charge Done Status
1b0 = Not Active 1b1 = Active |
4 | IINLIM_ACTIVE_STAT | R | X | Input Current Limit Status
1b0 = Not Active 1b1 = Active |
3 | VDPPM_ACTIVE_STAT | R | X | DPPM Status
1b0 = Not Active 1b1 = Active |
2 | VINDPM_ACTIVE_STAT | R | X | VINDPM Status
1b0 = Not Active 1b1 = Active |
1 | THERMREG_ACTIVE_STAT | R | X | Thermal Regulation Status
1b0 = Not Active 1b1 = Active |
0 | VIN_PGOOD_STAT | R | X | VIN Power Good Status
1b0 = Not Good 1b1 = VIN > VUVLO and VIN > VBAT + VSLP and VIN < VOVP |
STAT1 is shown in Figure 9-17 and described in Table 9-11.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VIN_OVP_FAULT_STAT | RESERVED | BAT_OCP_FAULT_STAT | BAT_UVLO_FAULT_STAT | TS_COLD_STAT | TS_COOL_STAT | TS_WARM_STAT | TS_HOT_STAT |
R-X | R-X | R-X | R-X | R-X | R-X | R-X | R-X |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | VIN_OVP_FAULT_STAT | R | X | VIN Overvoltage Status
1b0 = Not Active 1b1 = Active |
6 | RESERVED | R | X | Reserved |
5 | BAT_OCP_FAULT_STAT | R | X | Battery Over-Current Protection Status
1b0 = Not Active 1b1 = Active |
4 | BAT_UVLO_FAULT_STAT | R | X | Battery voltage below BATUVLO Level Status
1b0 = VBAT > VBATUVLO 1b1 = VBAT < VBATUVLO |
3 | TS_COLD_STAT | R | X | TS Cold Status - VTS > VCOLD (charging suspended)
1b0 = Not Active 1b1 = Active |
2 | TS_COOL_STAT | R | X | TS Cool Status - VCOOL < VTS < VCOLD (charging current reduced by value set by TS_Registers)
1b0 = Not Active 1b1 = Active |
1 | TS_WARM_STAT | R | X | TS Warm - VWARM > VTS >VHOT (charging voltage reduced by value set by TS_Registers)
1b0 = Not Active 1b1 = Active |
0 | TS_HOT_STAT | R | X | TS Hot Status - VTS < VHOT (charging suspended)
1b0 = Not Active 1b1 = Active |
STAT2 is shown in Figure 9-18 and described in Table 9-12.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COMP1_ALARM_STAT | COMP2_ALARM_STAT | COMP3_ALARM_STAT | RESERVED | TS_OPEN_STAT | ||
R-X | R-X | R-X | R-X | R-X | R-X | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | X | Reserved |
6 | COMP1_ALARM_STAT | R | X | COMP1 Status
1b0 = Selected ADC measurement does not meet condition set by 1_ADCALARM_ABOVE bit 1b1 = Selected ADC measurement meets condition set by 1_ADCALARM_ABOVE bit |
5 | COMP2_ALARM_STAT | R | X | COMP2 Status
1b0 = Selected ADC measurement does not meet condition set by 2_ADCALARM_ABOVE bit 1b1 = Selected ADC measurement meets condition set by 2_ADCALARM_ABOVE bit |
4 | COMP3_ALARM_STAT | R | X | COMP3 Status
1b0 = Selected ADC measurement does not meet condition set by 1_ADCALARM_ABOVE bit 1b1 = Selected ADC measurement meets condition set by 2_ADCALARM_ABOVE bit |
3-1 | RESERVED | R | X | Reserved |
0 | TS_OPEN_STAT | R | X | TS Open Status
1b0 = VTS < VOPEN 1b1 = VTS > VOPEN |
FLAG0 is shown in Figure 9-19 and described in Table 9-13.
Return to Summary Table.
Clear on Read
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CHRG_CV_FLAG | CHARGE_DONE_FLAG | IINLIM_ACTIVE_FLAG | VDPPM_ACTIVE_FLAG | VINDPM_ACTIVE_FLAG | THERMREG_ACTIVE_FLAG | VIN_PGOOD_FLAG |
RC-1b0 | RC-1b0 | RC-1b0 | RC-1b0 | RC-1b0 | RC-1b0 | RC-1b0 | RC-1b0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | RC | 1b0 | Reserved |
6 | CHRG_CV_FLAG | RC | 1b0 | Constant Voltage Charging Mode (Taper Mode) Flag
1b0 = CV Mode Entry not detected 1b1 = CV Mode Entry detected |
5 | CHARGE_DONE_FLAG | RC | 1b0 | Charge Done Flag
1b0 = Charge Done (Termination) not detected 1b1 = Charge Done (Termination) detected |
4 | IINLIM_ACTIVE_FLAG | RC | 1b0 | Input Current Limit Flag
1b0 = Input Current Limit not detected 1b1 = Input Current Limit detected |
3 | VDPPM_ACTIVE_FLAG | RC | 1b0 | DPPM Flag
1b0 = DPPM operation not detected 1b1 = DPPM operation detected |
2 | VINDPM_ACTIVE_FLAG | RC | 1b0 | VINDPM Flag
1b0 = VINDPM operation not detected 1b1 = VIINDPM operation detected |
1 | THERMREG_ACTIVE_FLAG | RC | 1b0 | Thermal Regulation Flag
1b0 = Thermal Regulation not detected 1b1 = Thermal Regulation detected |
0 | VIN_PGOOD_FLAG | RC | 1b0 | VIN Power Good Flag
1b0 = No change in VIN Power Good Status 1b1 = Change in VIN Power Good Status detected. |
FLAG1 is shown in Figure 9-20 and described in Table 9-14.
Return to Summary Table.
Clear on Read
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VIN_OVP_FAULT_FLAG | RESERVED | BAT_OCP_FAULT_FLAG | BAT_UVLO_FAULT_FLAG | TS_COLD_FLAG | TS_COOL_FLAG | TS_WARM_FLAG | TS_HOT_FLAG |
RC-1b0 | RC-1b0 | RC-1b0 | RC-1b0 | RC-1b0 | RC-1b0 | RC-1b0 | RC-1b0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | VIN_OVP_FAULT_FLAG | RC | 1b0 | VIN Over Voltage Fault Flag
1b0 = No overvoltage condition detected 1b1 = VIN overvoltage condition detected |
6 | RESERVED | RC | 1b0 | Reserved |
5 | BAT_OCP_FAULT_FLAG | RC | 1b0 | Battery Over Current Protection Flag
1b0 = No Battery Over Current condition detected 1b1 = Battery Over Current condition detected |
4 | BAT_UVLO_FAULT_FLAG | RC | 1b0 | Battery Under Voltage Flag
1b0 = Battery below BATUVLO condition detected 1b1 = No Battery below BATUVLO condition detected |
3 | TS_COLD_FLAG | RC | 1b0 | TS Cold Region Entry Flag
1b0 = TS Cold Region Entry not detected 1b1 = TS Cold Region Entry detected |
2 | TS_COOL_FLAG | RC | 1b0 | TS Cool Region Entry Flag
1b0 = TS Cool Region Entry not detected 1b1 = TS Co0l Region Entry detected |
1 | TS_WARM_FLAG | RC | 1b0 | TS Warm Region Entry Flag
1b0 = TS Warm Region Entry not detected 1b1 = TS Warm Region Entry detected |
0 | TS_HOT_FLAG | RC | 1b0 | TS Hot Region Entry Flag
1b0 = TS Hot Region Entry not detected 1b1 = TS Hot Region Entry detected |
FLAG2 is shown in Figure 9-21 and described in Table 9-15.
Return to Summary Table.
Clear on Read
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADC_READY_FLAG | COMP1_ALARM_FLAG | COMP2_ALARM_FLAG | COMP3_ALARM_FLAG | RESERVED | TS_OPEN_FLAG | ||
RC-1b0 | RC-1b0 | RC-1b0 | RC-1b0 | RC-3b000 | RC-1b0 | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | ADC_READY_FLAG | RC | 1b0 | ADC Ready Flag
1b0 = No ADC conversion completed since last flag read 1b1 = ADC Conversion Completed |
6 | COMP1_ALARM_FLAG | RC | 1b0 | ADC COMP1 Threshold Flag
1b0 = No threshold crossing detected 1b1 = Selected ADC measurement crossed condition set by 1_ADCALARM_ABOVE bit |
5 | COMP2_ALARM_FLAG | RC | 1b0 | ADC COMP2 Threshold Flag
1b0 = No threshold crossing detected 1b1 = Selected ADC measurement crossed condition set by 2_ADCALARM_ABOVE bit |
4 | COMP3_ALARM_FLAG | RC | 1b0 | ADC COMP3 Threshold Flag
1b0 = No threshold crossing detected 1b1 = Selected ADC measurement crossed condition set by 3_ADCALARM_ABOVE bit |
3-1 | RESERVED | RC | 3b000 | Reserved |
0 | TS_OPEN_FLAG | RC | 1b0 | TS Open Flag
1b0 = No TS Open fault detected 1b1 = TS Open fault detected |
FLAG3 is shown in Figure 9-22 and described in Table 9-16.
Return to Summary Table.
Clear on Read
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WD_FAULT_FLAG | SAFETY_TMR_FAULT_FLAG | LDO_OCP_FAULT_FLAG | RESERVED | MRWAKE1_TIMEOUT_FLAG | MRWAKE2_TIMEOUT_FLAG | MRRESET_WARN_FLAG |
RC-1b0 | RC-1b0 | RC-1b0 | RC-1b0 | RC-1b0 | RC-1b0 | RC-1b0 | RC-1b0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | RC | 1b0 | Reserved |
6 | WD_FAULT_FLAG | RC | 1b0 | Watchdog Fault Flag
1b0 = Watchdog Timer not expired 1b1 = Watchdog Timer expired |
5 | SAFETY_TMR_FAULT_FLAG | RC | 1b0 | Safety Timer Fault Flag
1b0 = Safety Timer not expired 1b1 = Safety Timer Expired |
4 | LDO_OCP_FAULT_FLAG | RC | 1b0 | LDO Over Current Fault
1b0 = LDO Normal 1b1 = LDO Over current fault detected |
2 | MRWAKE1_TIMEOUT_FLAG | RC | 1b0 | MR Wake 1 Timer Flag
1b0 = MR Wake 1 timer not expired 1b1 = MR Wake 1 timer expired |
1 | MRWAKE2_TIMEOUT_FLAG | RC | 1b0 | MR Wake 2 Timer Flag
1b0 = MR Wake 2 timer not expired 1b1 = MR Wake 2 timer expired |
0 | MRRESET_WARN_FLAG | RC | 1b0 | MR Reset Warn Timer Flag
1b0 = MR Reset Warn timer not expired 1b1 = MR Reset Warn timer expired |
MASK0 is shown in Figure 9-23 and described in Table 9-17.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CHRG_CV_MASK | CHARGE_DONE_MASK | IINLIM_ACTIVE_MASK | VDPPM_ACTIVE_MASK | VINDPM_ACTIVE_MASK | THERMREG_ACTIVE_MASK | VIN_PGOOD_MASK |
R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 1b0 | Reserved
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
6 | CHRG_CV_MASK | R/W | 1b0 | Mask for CHRG_CV interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
5 | CHARGE_DONE_MASK | R/W | 1b0 | Mask for CHARGE_DONE interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
4 | IINLIM_ACTIVE_MASK | R/W | 1b0 | Mask for IINLIM_ACTIVE interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
3 | VDPPM_ACTIVE_MASK | R/W | 1b0 | Mask for VDPPM_ACTIVE interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
2 | VINDPM_ACTIVE_MASK | R/W | 1b0 | Mask for VINDPM_ACTIVE interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
1 | THERMREG_ACTIVE_MASK | R/W | 1b0 | Mask for THERMREG_ACTIVE interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
0 | VIN_PGOOD_MASK | R/W | 1b0 | Mask for VIN_PGOOD interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
MASK1 is shown in Figure 9-24 and described in Table 9-18.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VIN_OVP_FAULT_MASK | RESERVED | BAT_OCP_FAULT_MASK | BAT_UVLO_FAULT_MASK | TS_COLD_MASK | TS_COOL_MASK | TS_WARM_MASK | TS_HOT_MASK |
R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | VIN_OVP_FAULT_MASK | R/W | 1b0 | Mask for VIN_OVP_FAULT interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
6 | RESERVED | R/W | 1b0 | Reserved |
5 | BAT_OCP_FAULT_MASK | R/W | 1b0 | Mask for BAT_OCP_FAULT interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
4 | BAT_UVLO_FAULT_MASK | R/W | 1b0 | Mask for BAT_UVLO_FAULT interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
3 | TS_COLD_MASK | R/W | 1b0 | Mask for TS_COLD interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
2 | TS_COOL_MASK | R/W | 1b0 | Mask for TS_COOL interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
1 | TS_WARM_MASK | R/W | 1b0 | Mask for TS_WARM interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
0 | TS_HOT_MASK | R/W | 1b0 | Mask for TS_HOT interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
MASK2 is shown in Figure 9-25 and described in Table 9-19.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADC_READY_FLAG | COMP1_ALARM_FLAG | COMP2_ALARM_FLAG | COMP3_ALARM_FLAG | RESERVED | TS_OPEN_MASK | ||
R/W-1b0 | R/W-1b1 | R/W-1b1 | R/W-1b1 | R/W-3b000 | R/W-1b1 | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | ADC_READY_MASK | R/W | 1b0 | Mask for ADC_READY Interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
6 | COMP1_ALARM_MASK | R/W | 1b1 | Mask for COMP1_ALARM Interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
5 | COMP2_ALARM_MASK | R/W | 1b1 | Mask for COMP2_ALARM Interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
4 | COMP3_ALARM_MASK | R/W | 1b1 | Mask for COMP3_ALARM Interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
3-1 | RESERVED | R/W | 3b000 | Reserved |
0 | TS_OPEN_MASK | R/W | 1b1 | Mask for TS_OPEN Interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
MASK3 is shown in Figure 9-26 and described in Table 9-20.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WD_FAULT_MASK | SAFETY_TMR_FAULT_MASK | LDO_OCP_FAULT_MASK | RESERVED | MRWAKE1_TIMEOUT_MASK | MRWAKE2_TIMEOUT_MASK | MRRESET_WARN_MASK |
R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 1b0 | Reserved |
6 | WD_FAULT_MASK | R/W | 1b0 | Mask for WD_FAULT Interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
5 | SAFETY_TMR_FAULT_MASK | R/W | 1b0 | Mask for SAFETY_TIMER_FAULT Interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
4 | LDO_OCP_FAULT_MASK | R/W | 1b0 | Mask for LDO_OCP_FAULT Interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
3 | RESERVED | R/W | 1b0 | Reserved |
2 | MRWAKE1_TIMEOUT_MASK | R/W | 1b0 | Mask for MRWAKE1_TIMEOUT Interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
1 | MRWAKE2_TIMEOUT_MASK | R/W | 1b0 | Mask for MRWAKE2_TIMEOUT Interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
0 | MRRESET_WARN_MASK | R/W | 1b0 | Mask for MRRESET_WARN Interrupt
1b0 = Interrupt Not Masked 1b1 = Interrupt Masked |
VBAT_CTRL is shown in Figure 9-27 and described in Table 9-21.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VBAT_REG_6:0 | ||||||
R/W-1b0 | R/W-7b0111100 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 1b0 | Reserved |
6-0 | VBAT_REG_6:0 | R/W | 7b0111100 | Battery Regulation Voltage (4.2 V default) VBATREG = 3.6 V + VBAT_REG code x 10 mV If a value greater than 4.6 V is written, the setting will go to 4.6 V |
ICHG_CTRL is shown in Figure 9-28 and described in Table 9-22.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ICHG_7:0 | |||||||
R/W-8b00001000 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | ICHG_7:0 | R/W | 8b00001000 | Fast Charge Current (10 mA default) Fast Charge Current = 1.25 mA x ICHG code (ICHARGE_RANGE = 0) Fast Charge Current = 2.5 mA x ICHG code (ICHARGE_RANGE = 1) |
PCHRGCTRL is shown in Figure 9-29 and described in Table 9-23.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ICHARGE_RANGE | RESERVED | IPRECHG_4:0 | |||||
R/W-1b0 | R/W-2b00 | R/W-5b00010 | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | ICHARGE_RANGE | R/W | 1b0 | Charge Current Step 1b0 = 1.25 mA step (318.75 mA max charge current) 1b1 = 2.5 mA step (500 mA max charge current) |
6-5 | RESERVED | R/W | 2b00 | Reserved |
4-0 | IPRECHG_4:0 | R/W | 5b00010 | Pre-Charge Current (2.5 mA default) Pre-Charge Current = 1.25 mA x IPRECHG code (ICHARGE_RANGE = 0) Pre-Charge Current = 2.5 mA x IPRECHG code (ICHARGE_RANGE = 1) |
TERMCTRL is shown in Figure 9-30 and described in Table 9-24.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ITERM_4:0 | TERM_DISABLE | |||||
R/W-2b00 | R/W-5b01010 | R/W-1b0 | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R/W | 2b00 | Reserved |
5-1 | ITERM_4:0 | R/W | 5b01010 | Termination Current (10% of ICHRG default) Programmable Range = 1% to 31% of ICHRG 5b00000 = Do not Use 5b00001 = 1% of ICHRG 5b00010 = 2% of ICHRG 5b00100 = 4% of ICHRG 5b01000 = 8% of ICHRG 5b10000 = 16% of ICHRG |
0 | TERM_DISABLE | R/W | 1b0 | Termination Disable
1b0 = Termination Enabled 1b1 = Termination Disabled |
BUVLO is shown in Figure 9-31 and described in Table 9-25.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VLOWV_SEL | IBAT_OCP_ILIM_1:0 | BUVLO_2:0 | ||||
R/W-2b00 | R/W-1b0 | R/W-2b00 | R/W-3b000 | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R/W | 2b00 | Reserved |
5 | VLOWV_SEL | R/W | 1b0 | Pre-charge to Fast Charge Threshold
1b0 = 3.0 V 1b1 = 2.8 V |
4-3 | IBAT_OCP_ILIM_1:0 | R/W | 2b00 | Battery Over-Current Protection Threshold
2b00 = 1200 mA 2b01 = 1500 mA 2b10 = Disabled 2b11 = Disabled |
2-0 | BUVLO_2:0 | R/W | 3b000 | Battery UVLO Voltage
3b000 = 3.0 V 3b001 = 3.0 V 3b010 = 3.0 V 3b011 = 2.8 V 3b100 = 2.6 V 3b101 = 2.4 V 3b110 = 2.2 V 3b111 = Disabled |
CHARGERCTRL0 is shown in Figure 9-32 and described in Table 9-26.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_EN | TS_CONTROL_MODE | VRH_THRESH | WATCHDOG_DISABLE | 2XTMR_EN | SAFETY_TIMER_LIMIT_1:0 | RESERVED | |
R/W-1b1 | R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-2b01 | R/W-1b0 | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | TS_EN | R/W | 1b1 | TS Function Enable
1b0 = TS function disabled (Only charge control is disabled. TS_OPEN detection and TS ADC monitoring remain enabled) 1b1 = TS function enabled |
6 | TS_CONTROL_MODE | R/W | 1b0 | TS Function Control Mode
1b0 = Custom (JEITA) 1b1 = Disable charging on HOT/COLD Only |
5 | VRH_THRESH | R/W | 1b0 | Recharge Voltage Threshold
1b0 = 140 mV 1b1 = 200 mV |
4 | WATCHDOG_DISABLE | R/W | 1b0 | Watchdog Timer Disable
1b0 = Watchdog timer enabled 1b1 = Watchdog timer disabled |
3 | 2XTMR_EN | R/W | 1b0 | Enable 2X Safety Timer
1b0 = The timer is not slowed at any time 1b1 = The timer is slowed by 2x when in any control other than CC or CV |
2-1 | SAFETY_TIMER_LIMIT_1:0 | R/W | 2b01 | Charger Safety Timer
2b00 = 3 Hr Fast Charge 2b01 = 6 Hr Fast Charge 2b10 = 12 Hr Fast Charge 2b11 = Disabled |
0 | RESERVED | R/W | 1b0 | Reserved |
CHARGERCTRL1 is shown in Figure 9-33 and described in Table 9-27.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VINDPM_DIS | VINPDM_2:0 | DPPM_DIS | THERM_REG_2:0 | ||||
R/W-1b1 | R/W-3b100 | R/W-1b0 | R/W-3b010 | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | VINDPM_DIS | R/W | 1b1 | Disable VINDPM Function
1b0 = VINDPM Enabled 1b1 = VINDPM Disabled |
6-4 | VINPDM_2:0 | R/W | 3b100 | VINDPM Level Selection
3b000 = 4.2 V 3b001 = 4.3 V 3b010 = 4.4 V 3b011 = 4.5 V 3b100 = 4.6 V 3b101 = 4.7 V 3b110 = 4.8 V 3b111 = 4.9 V |
3 | DPPM_DIS | R/W | 1b0 | DPPM Disable
1b0 = DPPM function enabled 1b1 = DPPM function disabled |
2-0 | THERM_REG_2:0 | R/W | 3b010 | Thermal Charge Current Foldback Threshold
3b000 = 80°C 3b001 = 85°C 3b010 = 90°C 3b011 = 95°C 3b100 = 100°C 3b101 = 105°C 3b110 = 110°C 3b111 = Disabled |
ILIMCTRL is shown in Figure 9-34 and described in Table 9-28.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ILIM_2:0 | ||||||
R/W-5b00000 | R/W-3b110 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | RESERVED | R/W | 5b00000 | Reserved |
2-0 | ILIM_2:0 | R/W | 3b110 | Input Current Limit Level Selection
3b000 = 50 mA 3b001 = 100 mA 3b010 = 150 mA 3b011 = 200 mA 3b100 = 300 mA 3b101 = 400 mA 3b110 = 500 mA 3b111 = 600 mA |
LDOCTRL is shown in Figure 9-35 and described in Table 9-29.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN_LS_LDO | VLDO_4:0 | LDO_SWITCH_CONFG | RESERVED | ||||
R/W-1b1 | R/W-5b01100 | R/W-1b0 | R/W-1b0 | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | EN_LS_LDO | R/W | 1b1 | LS/LDO Enable
1b0 = Disable LS/LDO 1b1 = Enable LS/LDO |
6-2 | VLDO_4:0 | R/W | 5b01100 | LDO output voltage setting (1.8 V default) LDO Voltage = 600 mV + VLDO Code x 100 mV |
1 | LDO_SWITCH_CONFG | R/W | 1b0 | LDO / Load Switch Configuration Select
1b0 = LDO 1b1 = Load Switch |
0 | RESERVED | R/W | 1b0 | Reserved |
MRCTRL is shown in Figure 9-36 and described in Table 9-30.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MR_RESET_VIN | MR_WAKE1_TIMER | MR_WAKE2_TIMER | MR_RESET_WARN_1:0 | MR_HW_RESET_1:0 | RESERVED | ||
R/W-1b0 | R/W-1b0 | R/W-1b1 | R/W-2b01 | R/W-2b01 | R/W-1b0 | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | MR_RESET_VIN | R/W | 1b0 | VIN Power Good gated MR Reset Enable
1b0 = Reset sent when /MR reset time is met regardless of VIN state 1b1 = Reset sent when MR reset is met and Vin is valid |
6 | MR_WAKE1_TIMER | R/W | 1b0 | Wake 1 Timer setting
1b0 = 125 ms 1b1 = 500 ms |
5 | MR_WAKE2_TIMER | R/W | 1b1 | Wake 2 Timer setting
1b0 = 1 s 1b1 = 2 s |
4-3 | MR_RESET_WARN_1:0 | R/W | 2b01 | MR Reset Warn Timer setting
2b00 = MR_HW_RESET - 0.5 s 2b01 = MR_HW_RESET - 1.0 s 2b10 = MR_HW_RESET - 1.5 s 2b11 = MR_HW_RESET - 2.0 s |
2-1 | MR_HW_RESET_1:0 | R/W | 2b01 | MR HW Reset Timer setting
2b00 = 4 s 2b01 = 8 s 2b10 = 10 s 2b11 = 14 s |
0 | RESERVED | R/W | 1b0 | Reserved |
ICCTRL0 is shown in Figure 9-37 and described in Table 9-31.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN_SHIP_MODE | RESERVED | AUTOWAKE_1:0 | RESERVED | GLOBAL_INT_MASK | HW_RESET | SW_RESET | |
R/W-1b0 | R/W-1b0 | R/W-2b01 | R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | EN_SHIP_MODE | R/W | 1b0 | Ship Mode Enable
1b0 = Normal operation 1b1 = Enter Ship Mode when VIN is not valid and /MR is high |
6 | RESERVED | R/W | 1b0 | Reserved |
5-4 | AUTOWAKE_1:0 | R/W | 2b01 | Auto-wakeup Timer (TRESTART) for /MR HW Reset
2b00 = 0.6 s 2b01 = 1.2 s 2b10 = 2.4 s 2b11 = 5 s |
3 | RESERVED | R/W | 1b0 | Reserved |
2 | GLOBAL_INT_MASK | R/W | 1b0 | Global Interrupt Mask
1b0 = Normal Operation 1b1 = Mask all interrupts |
1 | HW_RESET | R/W | 1b0 | HW Reset
1b0 = Normal operation 1b1 = HW Reset. Temporarily power down all power rails, except VDD. I2C Register go to default settings. |
0 | SW_RESET | R/W | 1b0 | SW_Reset
1b0 = Normal operation 1b1 = SW Reset. I2C Registers go to default settings. |
ICCTRL1 is shown in Figure 9-38 and described in Table 9-32.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MR_LPRESS_ACTION_1:0 | ADCIN_MODE | RESERVED | PG_MODE_1:0 | PMID_MODE_1:0 | |||
R/W-2b00 | R/W-1b0 | R/W-1b0 | R/W-2b00 | R/W-2b00 | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | MR_LPRESS_ACTION_1:0 | R/W | 2b00 | MR Long Press Action
2b00 = HW Reset (Power Cycle) 2b01 = Do nothing 2b10 = Enter Ship Mode 2b11 = Enter Ship Mode |
5 | ADCIN_MODE | R/W | 1b0 | ADCIN Pin Mode of Operation
1b0 = General Purpose ADC input (no Internal biasing) 1b1 = 10K NTC ADC input (80 µA biasing) |
4 | RESERVED | R/W | 1b0 | Reserved |
3-2 | PG_MODE_1:0 | R/W | 2b00 | PG Pin Mode of Operation
2b00 = VIN Power Good 2b01 = Deglitched Level Shifted /MR 2b10 = General Purpose Open Drain Output 2b11 = General Purpose Open Drain Output |
1-0 | PMID_MODE_1:0 | R/W | 2b00 | PMID Control Sets how PMID is powered in any state, except Ship Mode. 2b00 = PMID powered from BAT or VIN if present 2b01 = PMID powered from BAT only, even if VIN is present 2b10 = PMID disconnected and left floating 2b11 = PMID disconnected and pulled down. |
ICCTRL2 is shown in Figure 9-39 and described in Table 9-33.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PMID_REG_CTRL_2:0 | GPO_PG | RESERVED | HWRESET_14S_WD | CHARGER_DISABLE | |||
R/W-3b010 | R/W-1b0 | R/W-2b00 | R/W-1b0 | R/W-1b0 | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | PMID_REG_CTRL_2:0 | R/W | 3b010 | System (PMID) Regulation Voltage
3b000 = Battery Tracking 3b001 = 4.4 V 3b010 = 4.5 V 3b011 = 4.6 V 3b100 = 4.7 V 3b101 = 4.8 V 3b110 = 4.9 V 3b111 = Pass-Through (VIN) |
4 | GPO_PG | R/W | 1b0 | /PG General Purpose Output State Control
1b0 = Pulled Down 1b1 = High Z |
3-2 | RESERVED | R/W | 2b00 | Reserved |
1 | HWRESET_14S_WD | R/W | 1b0 | Enable for 14-second I2C watchdog timer for HW Reset after VIN connection
1b0 = Timer disabled 1b1 = Device will perform HW reset if no I2C transaction is done within 14 s after VIN is present |
0 | CHARGER_DISABLE | R/W | 1b0 | Charge Disable
1b0 = Charge enabled if /CE pin is low 1b1 = Charge disabled |
ADCCTRL0 is shown in Figure 9-40 and described in Table 9-34.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADC_READ_RATE_1:0 | ADC_CONV_START | ADC_CONV_SPEED_1:0 | ADC_COMP1_2:0 | ||||
R/W-2b00 | R/W-1b0 | R/W-2b00 | R/W-3b010 | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | ADC_READ_RATE_1:0 | R/W | 2b00 | Read rate for ADC measurements in BAT Only operation
2b00 = Manual Read (Measurement done when ADC_CONV_START is set) 2b01 = Continuous 2b10 = Every 1 second 2b11 = Every 1 minute |
5 | ADC_CONV_START | R/W | 1b0 | ADC Conversion Start Trigger Bit goes back to 0 when conversion is complete 1b0 = No ADC conversion 1b1 = Initiates ADC measurement in Manual Read operation |
4-3 | ADC_CONV_SPEED_1:0 | R/W | 2b00 | ADC Conversion Speed
2b00 = 24 ms (highest accuracy) 2b01 = 12 ms 2b10 = 6 ms 2b11 = 3 ms |
2-0 | ADC_COMP1_2:0 | R/W | 3b010 | ADC Channel for Comparator 1
3b000 = Disabled 3b001 = ADCIN 3b010 = TS 3b011 = VBAT 3b100 = ICHARGE 3b101 = VIN 3b110 = PMID 3b111 = IIN |
ADCCTRL1 is shown in Figure 9-41 and described in Table 9-35.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADC_COMP2_2:0 | ADC_COMP3_2:0 | RESERVED | |||||
R/W-3b010 | R/W-3b000 | R/W-2b00 | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | ADC_COMP2_2:0 | R/W | 3b010 | ADC Channel for Comparator 2
3b000 = Disabled 3b001 = ADCIN 3b010 = TS 3b011 = VBAT 3b100 = ICHARGE 3b101 = VIN 3b110 = PMID 3b111 = IIN |
4-2 | ADC_COMP3_2:0 | R/W | 3b000 | ADC Channel for Comparator 3
3b000 = Disabled 3b001 = ADCIN 3b010 = TS 3b011 = VBAT 3b100 = ICHARGE 3b101 = VIN 3b110 = PMID 3b111 = IIN |
1-0 | RESERVED | R/W | 2b00 | Reserved |
ADC_DATA_VBAT_M is shown in Figure 9-42 and described in Table 9-36.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VBAT_ADC_15:8 | |||||||
R-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | VBAT_ADC_15:8 | R | X | ADC VBAT Measurement MSB |
ADC_DATA_VBAT_L is shown in Figure 9-43 and described in Table 9-37.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VBAT_ADC_7:0 | |||||||
R-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | VBAT_ADC_7:0 | R | X | ADC VBAT Measurement LSB |
ADC_DATA_TS_M is shown in Figure 9-44 and described in Table 9-38.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_ADC_15:8 | |||||||
R-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | TS_ADC_15:8 | R | X | ADC TS Measurement MSB |
ADC_DATA_TS_L is shown in Figure 9-45 and described in Table 9-39.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_ADC_7:0 | |||||||
R-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | TS_ADC_7:0 | R | X | ADC TS Measurement LSB |
ADC_DATA_ICHG_M is shown in Figure 9-46 and described in Table 9-40.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ICHG_ADC_15:8 | |||||||
R-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | ICHG_ADC_15:8 | R | X | ADC ICHG Measurement MSB |
ADC_DATA_ICHG_L is shown in Figure 9-47 and described in Table 9-41.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ICHG_ADC_7:0 | |||||||
R-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | ICHG_ADC_7:0 | R | X | ADC ICHG Measurement LSB |
ADC_DATA_ADCIN_M is shown in Figure 9-48 and described in Table 9-42.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADCIN_ADC_15:8 | |||||||
R-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | ADCIN_ADC_15:8 | R | X | ADC ADCIN Measurement MSB |
ADC_DATA_ADCIN_L is shown in Figure 9-49 and described in Table 9-43.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADCIN_ADC_7:0 | |||||||
R-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | ADCIN_ADC_7:0 | R | X | ADC ADCIN Measurement LSB |
ADC_DATA_VIN_M is shown in Figure 9-50 and described in Table 9-44.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VIN_ADC_15:8 | |||||||
R-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | VIN_ADC_15:8 | R | X | ADC VIN Measurement MSB |
ADC_DATA_VIN_L is shown in Figure 9-51 and described in Table 9-45.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VIN_ADC_7:0 | |||||||
R-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | VIN_ADC_7:0 | R | X | ADC VIN Measurement LSB |
ADC_DATA_PMID_M is shown in Figure 9-52 and described in Table 9-46.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PMID_ADC_15:8 | |||||||
R-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | PMID_ADC_15:8 | R | X | ADC PMID Measurement MSB |
ADC_DATA_PMID_L is shown in Figure 9-53 and described in Table 9-47.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PMID_ADC_7:0 | |||||||
R-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | PMID_ADC_7:0 | R | X | ADC PMID Measurement LSB |
ADC_DATA_IIN_M is shown in Figure 9-54 and described in Table 9-48.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IIN_ADC_15:8 | |||||||
R-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | IIN_ADC_15:8 | R | X | ADC IIN Measurement MSB |
ADC_DATA_IIN_L is shown in Figure 9-55 and described in Table 9-49.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IIN_ADC_7:0 | |||||||
R-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | IIN_ADC_7:0 | R | X | ADC IIN Measurement LSB |
ADCALARM_COMP1_M is shown in Figure 9-56 and described in Table 9-50.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1_ADCALARM_15:8 | |||||||
R/W-8b00100011 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | 1_ADCALARM_15:8 | R/W | 8b00100011 | ADC Comparator 1 Threshold MSB |
ADCALARM_COMP1_L is shown in Figure 9-57 and described in Table 9-51.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1_ADCALARM_7:4 | 1_ADCALARM_ABOVE | RESERVED | |||||
R/W-4b0010 | R/W-1b0 | R/W-3b000 | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | 1_ADCALARM_7:4 | R/W | 4b0010 | ADC Comparator 1 Threshold LSB |
3 | 1_ADCALARM_ABOVE | R/W | 1b0 | ADC Comparator1 Polarity
1b0 = Set Flag and send interrupt if ADC measurement becomes lower than comparator threshold 1b1 = Set Flag and send interrupt if ADC measurement is becomes higher than comparator threshold |
2-0 | RESERVED | R/W | 3b000 | Reserved |
ADCALARM_COMP2_M is shown in Figure 9-58 and described in Table 9-52.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
2_ADCALARM_15:8 | |||||||
R/W-8b00111000 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | 2_ADCALARM_15:8 | R/W | 8b00111000 | ADC Comparator 2 Threshold MSB |
ADCALARM_COMP2_L is shown in Figure 9-59 and described in Table 9-53.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
2_ADCALARM_7:4 | 2_ADCALARM_ABOVE | RESERVED | |||||
R/W-4b1001 | R/W-1b0 | R/W-3b000 | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | 2_ADCALARM_7:4 | R/W | 4b1001 | ADC Comparator 2 Threshold LSB |
3 | 2_ADCALARM_ABOVE | R/W | 1b0 | ADC Comparator 2 Polarity
1b0 = Set Flag and send interrupt if ADC measurement becomes lower than comparator threshold 1b1 = Set Flag and send interrupt if ADC measurement is becomes higher than comparator threshold |
2-0 | RESERVED | R/W | 3b000 | Reserved |
ADCALARM_COMP3_M is shown in Figure 9-60 and described in Table 9-54.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
3_ADCALARM_15:8 | |||||||
R/W-8b00000000 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | 3_ADCALARM_15:8 | R/W | 8b00000000 | ADC Comparator 3 Threshold MSB |
ADCALARM_COMP3_L is shown in Figure 9-61 and described in Table 9-55.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
3_ADCALARM_7:4 | 3_ADCALARM_ABOVE | RESERVED | |||||
R/W-4b0000 | R/W-1b0 | R/W-3b000 | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | 3_ADCALARM_7:4 | R/W | 4b0000 | ADC Comparator 3 Threshold LSB |
3 | 3_ADCALARM_ABOVE | R/W | 1b0 | ADC Comparator 3 Polarity
1b0 = Set Flag and send interrupt if ADC measurement becomes lower than comparator threshold 1b1 = Set Flag and send interrupt if ADC measurement is becomes higher than comparator threshold |
2-0 | RESERVED | R/W | 3b000 | Reserved |
ADC_READ_EN is shown in Figure 9-62 and described in Table 9-56.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN_IIN_READ | EN_PMID_READ | EN_ICHG_READ | EN_VIN_READ | EN_VBAT_READ | EN_TS_READ | EN_ADCIN_READ | RESERVED |
R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 | R/W-1b0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | EN_IIN_READ | R/W | 1b0 | Enable measurement for Input Current (IIN) Channel
1b0 = ADC measurement disabled 1b1 = ADC measurement enabled |
6 | EN_PMID_READ | R/W | 1b0 | Enable measurement for PMID Channel
1b0 = ADC measurement disabled 1b1 = ADC measurement enabled |
5 | EN_ICHG_READ | R/W | 1b0 | Enable measurement for Charge Current Channel
1b0 = ADC measurement disabled 1b1 = ADC measurement enabled |
4 | EN_VIN_READ | R/W | 1b0 | Enable measurement for Input Voltage (VIN) Channel
1b0 = ADC measurement disabled 1b1 = ADC measurement enabled |
3 | EN_VBAT_READ | R/W | 1b0 | Enable measurement for Battery Voltage (VBAT) Channel
1b0 = ADC measurement disabled 1b1 = ADC measurement enabled |
2 | EN_TS_READ | R/W | 1b0 | Enable measurement for TS Channel
1b0 = ADC measurement disabled 1b1 = ADC measurement enabled |
1 | EN_ADCIN_READ | R/W | 1b0 | Enable measurement for ADCIN Channel
1b0 = ADC measurement disabled 1b1 = ADC measurement enabled |
0 | RESERVED | R/W | 1b0 | Reserved |
TS_FASTCHGCTRL is shown in Figure 9-63 and described in Table 9-57.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_VBAT_REG__2:0 | RESERVED | TS_ICHRG_2:0 | ||||
R/W-1b0 | R/W-3b011 | R/W-1b0 | R/W-3b100 | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 1b0 | Reserved |
6-4 | TS_VBAT_REG__2:0 | R/W | 3b011 | Reduced target battery voltage during Warm
3b000 = No reduction 3b001 = VBAT_REG - 50 mV 3b010 = VBAT_REG - 100 mV 3b011 = VBAT_REG - 150 mV 3b100 = VBAT_REG - 200 mV 3b101 = VBAT_REG - 250 mV 3b110 = VBAT_REG - 300 mV 3b111 = VBAT_REG - 350 mV |
3 | RESERVED | R/W | 1b0 | Reserved |
2-0 | TS_ICHRG_2:0 | R/W | 3b100 | Fast charge current when decreased by TS function
3b000 = No reduction 3b001 = 0.875 x ICHG 3b010 = 0.750 x ICHG 3b011 = 0.625 x ICHG 3b100 = 0.500 x ICHG 3b101 = 0.375 x ICHG 3b110 = 0.250 x ICHG 3b111 = 0.125 x ICHG |
TS_COLD is shown in Figure 9-64 and described in Table 9-58.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_COLD_7:0 | |||||||
R/W-8b01111100 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | TS_COLD_7:0 | R/W | 8b01111100 | TS Cold Threshold
1b = 4.688 mV 10b = 9.375 mV 100b = 18.75 mV 1000b = 37.5 mV 10000b = 75 mV 100000b = 150 mV 1000000b = 300 mV 10000000b = 600 mV |
TS_COOL is shown in Figure 9-65 and described in Table 9-59.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_COOL_7:0 | |||||||
R/W-8b01101101 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | TS_COOL_7:0 | R/W | 8b01101101 | TS Cool Threshold
1b = 4.688 mV 10b = 9.375 mV 100b = 18.75 mV 1000b = 37.5 mV 10000b = 75 mV 100000b = 150 mV 1000000b = 300 mV 10000000b = 600 mV |
TS_WARM is shown in Figure 9-66 and described in Table 9-60.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_WARM_7:0 | |||||||
R/W-8b00111000 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | TS_WARM_7:0 | R/W | 8b00111000 | TS Warm Threshold
1b = 4.688 mV 10b = 9.375 mV 100b = 18.75 mV 1000b = 37.5 mV 10000b = 75 mV 100000b = 150 mV 1000000b = 300 mV 10000000b = 600 mV |
TS_HOT is shown in Figure 9-67 and described in Table 9-61.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_HOT_7:0 | |||||||
R/W-8b00100111 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | TS_HOT_7:0 | R/W | 8b00100111 | TS Hot Threshold
1b = 4.688 mV 10b = 9.375 mV 100b = 18.75 mV 1000b = 37.5 mV 10000b = 75 mV 100000b = 150 mV 1000000b = 300 mV 10000000b = 600 mV |
DEVICE_ID is shown in Figure 9-68 and described in Table 9-62.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEVICE_ID_7:0 | |||||||
R-8b00110101 | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DEVICE_ID_7:0 | R | 8b00110101 | Device ID
110101b = BQ25155 |