SLUSF69 May   2024 BQ25186

ADVANCE INFORMATION  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Timing Requirements
  8. Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Battery Charging Process
        1. 7.1.1.1 Trickle Charge
        2. 7.1.1.2 Pre-Charge
        3. 7.1.1.3 Fast Charge
        4. 7.1.1.4 Termination
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Based Dynamic Power Management (VINDPM)
      2. 7.3.2  Dynamic Power Path Management Mode (DPPM)
      3. 7.3.3  Battery Supplement Mode
      4. 7.3.4  Sleep Mode
      5. 7.3.5  SYS Power Control (SYS_MODE bit control)
        1. 7.3.5.1 SYS Pulldown Control
      6. 7.3.6  SYS Regulation
      7. 7.3.7  Input Current Limit (ILIM)
      8. 7.3.8  Protection Mechanisms
        1. 7.3.8.1 Input Overvoltage Protection
        2. 7.3.8.2 Battery Undervoltage Lockout
        3. 7.3.8.3 Battery Overcurrent Protection
        4. 7.3.8.4 System Overvoltage Protection
        5. 7.3.8.5 System Short Protection
        6. 7.3.8.6 Thermal Protection and Thermal Regulation
        7. 7.3.8.7 Safety Timer and Watchdog Timer
      9. 7.3.9  Pushbutton Wake and Reset Input
        1. 7.3.9.1 Pushbutton Wake or Short Button Press Functions
        2. 7.3.9.2 Pushbutton Reset or Long Button Press Functions
      10. 7.3.10 Hardware Reset
      11. 7.3.11 Software Reset
      12. 7.3.12 Interrupt Indicator (/INT) Pin
        1. 7.3.12.1 Interrupt Indicator (/INT) Pin
      13. 7.3.13 Power Good (PG) / General Purpose Output Pin
      14. 7.3.14 External NTC Monitoring (TS)
        1. 7.3.14.1 TS Biasing and Function
      15. 7.3.15 I2C Interface
        1. 7.3.15.1 F/S Mode Protocol
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
      1. 7.5.1 I2C Registers
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input (IN/SYS) Capacitors
        2. 8.2.2.2 TS
        3. 8.2.2.3 Recommended Passive Components
  10. Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DLH|10
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Battery Charging Process

When a valid input source is connected (VIN > VINDPM and VBAT +VSLEEP < VIN < VIN_OVP), the state of the CE pin, CHARGE_DISABLE bit, and the TS/MR pin determines whether a charge cycle is initiated. When the CE pin or the CHARGE_DISABLE bit is set to disable charging, VHOT < VTS/MR < VCOLD and a valid input source is connected, the battery FET is turned off, preventing any kind of charging of the battery. Note that supplement behavior is independent of the CE pin or CHARGE_DISABLE bit. The device will be able to charge a battery as long as VIN voltage is higher than the VIN_LOWV threshold or VINDPM if enabled. This threshold is present as the VIN can be considered "powergood" with a very low battery voltage or a 0-V battery.

For devices with a dedicated CE pin, if either the charge disable bit is set to disable charging or the CE pin is high, the device will shut off charging to the battery. Both have to be set to enabled for charging to occur.

The following figure illustrates a typical charge cycle.

BQ25186 Charger Flow DiagramFigure 7-1 Charger Flow Diagram