SLUSEG2C September   2022  – February 2024 BQ25620 , BQ25622

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power-On-Reset (POR)
      2. 8.3.2  Device Power Up from Battery
      3. 8.3.3  Device Power Up from Input Source
        1. 8.3.3.1 REGN LDO Power Up
        2. 8.3.3.2 Poor Source Qualification
        3. 8.3.3.3 D+/D– Detection Sets Input Current Limit (BQ25620 Only)
        4. 8.3.3.4 ILIM Pin (BQ25622 Only)
        5. 8.3.3.5 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        6. 8.3.3.6 Converter Power-Up
      4. 8.3.4  Power Path Management
        1. 8.3.4.1 Narrow VDC Architecture
        2. 8.3.4.2 Dynamic Power Management
        3. 8.3.4.3 High Impedance Mode
      5. 8.3.5  Battery Charging Management
        1. 8.3.5.1 Autonomous Charging Cycle
        2. 8.3.5.2 Battery Charging Profile
        3. 8.3.5.3 Charging Termination
        4. 8.3.5.4 Thermistor Qualification
          1. 8.3.5.4.1 Advanced Temperature Profile in Charge Mode
          2. 8.3.5.4.2 TS Pin Thermistor Configuration
          3. 8.3.5.4.3 Cold/Hot Temperature Window in OTG Mode
          4. 8.3.5.4.4 JEITA Charge Rate Scaling
          5. 8.3.5.4.5 TS_BIAS Pin (BQ25622 Only)
        5. 8.3.5.5 Charging Safety Timers
      6. 8.3.6  USB On-The-Go (OTG)
        1. 8.3.6.1 Boost OTG Mode
      7. 8.3.7  Integrated 12-Bit ADC for Monitoring
      8. 8.3.8  Status Outputs ( PG, STAT, INT)
        1. 8.3.8.1 PG Pin Power Good Indicator
        2. 8.3.8.2 Interrupts and Status, Flag and Mask Bits
        3. 8.3.8.3 Charging Status Indicator (STAT)
        4. 8.3.8.4 Interrupt to Host ( INT)
      9. 8.3.9  BATFET Control
        1. 8.3.9.1 Shutdown Mode
        2. 8.3.9.2 Ship Mode
        3. 8.3.9.3 System Power Reset
      10. 8.3.10 Protections
        1. 8.3.10.1 Voltage and Current Monitoring in Battery Only and HIZ Modes
          1. 8.3.10.1.1 Battery Undervoltage Lockout
          2. 8.3.10.1.2 Battery Overcurrent Protection
        2. 8.3.10.2 Voltage and Current Monitoring in Buck Mode
          1. 8.3.10.2.1 Input Overvoltage
          2. 8.3.10.2.2 System Overvoltage Protection (SYSOVP)
          3. 8.3.10.2.3 Forward Converter Cycle-by-Cycle Current Limit
          4. 8.3.10.2.4 System Short
          5. 8.3.10.2.5 Battery Overvoltage Protection (BATOVP)
          6. 8.3.10.2.6 Sleep and Poor Source Comparators
        3. 8.3.10.3 Voltage and Current Monitoring in Boost Mode
          1. 8.3.10.3.1 Boost Mode Overvoltage Protection
          2. 8.3.10.3.2 Boost Mode Duty Cycle Protection
          3. 8.3.10.3.3 Boost Mode PMID Undervoltage Protection
          4. 8.3.10.3.4 Boost Mode Battery Undervoltage
          5. 8.3.10.3.5 Boost Converter Cycle-by-Cycle Current Limit
          6. 8.3.10.3.6 Boost Mode SYS Short
        4. 8.3.10.4 Thermal Regulation and Thermal Shutdown
          1. 8.3.10.4.1 Thermal Protection in Buck Mode
          2. 8.3.10.4.2 Thermal Protection in Boost Mode
          3. 8.3.10.4.3 Thermal Protection in Battery-Only Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
      2. 8.4.2 Register Bit Reset
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 START and STOP Conditions
        3. 8.5.1.3 Byte Format
        4. 8.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.5.1.5 Target Address and Data Direction Bit
        6. 8.5.1.6 Single Write and Read
        7. 8.5.1.7 Multi-Write and Multi-Read
    6. 8.6 Register Maps
      1. 8.6.1 Register Programming
      2. 8.6.2 BQ25620 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.2 Input Capacitor

Design input capacitance to provide enough ripple current rating to absorb input switching ripple current. The worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS current ICin occurs where the duty cycle is closest to 50% and can be estimated using Equation 5.

Equation 5. GUID-5F9A1422-9980-4EC2-B823-A0D3A0264FEC-low.gif

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be placed as close as possible to the drain of the high-side MOSFET (PMID) and source of the low-side MOSFET (GND). Voltage rating of the capacitor must be higher than normal input voltage level. A rating of 25-V or higher capacitor is preferred for 15 V input voltage. 10-μF ceramic capacitor is suggested for typical of 3.5A charging current.