SLUSFB0 August 2024 BQ25758S
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The device is a host controlled converter, but it can operate in default mode without host management. In default mode, the device can be used as an autonomous converter with no host or while host is in sleep mode. When the converter is in default mode, WD_STAT bit becomes HIGH, WD_FLAG is set to 1, and a INT is asserted low to alert the host (unless masked by WD_MASK). The WD_FLAG bit would read as a '1' upon the first read and then '0' upon subsequent reads. When the converter is in host mode, WD_STAT bit is LOW.
After power-on-reset, the device starts in default mode with watchdog timer expired. All the registers are in the default settings.
In default mode, the device regulates the output voltage to 5 V, with current limit as set by the IOUT pin (refer to Section 7.3.4.2).
A write to any I2C register transitions the converter from default mode to host mode, and initiates the watchdog timer. All the device parameters can be programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by writing 1 to WD_RST bit before the watchdog timer expires (WD_STAT bit is set), or disable watchdog timer by setting WATCHDOG bits = 00.
When the watchdog timer is expired, the device returns to default mode and select registers are reset to default values as detailed in the Register Map section. The Watchdog timer will be reset on any write if the watchdog timer has expired. When watchdog timer expires, WD_STAT and WD_FLAG is set to 1, and /INT is asserted low to alert the host (unless masked by WD_MASK).