SLUSFB0 August 2024 BQ25758S
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Table 7-3 lists the memory-mapped registers for the BQ25758S registers. All register offset addresses not listed in Table 7-3 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Register Name | Section |
---|---|---|---|
0x2 | REG0x02_Output_Current_Limit | Output Current Limit | Go |
0x4 | REG0x04_Output_Voltage_Limit | Output Voltage Limit | Go |
0x6 | REG0x06_Input_Current_DPM_Limit | Input Current DPM Limit | Go |
0x8 | REG0x08_Input_Voltage_DPM_Limit | Input Voltage DPM Limit | Go |
0xA | REG0x0A_Reverse_Mode_Input_Current_Limit | Reverse Mode Input Current Limit | Go |
0xC | REG0x0C_Reverse_Mode_Input_Voltage_Limit | Reverse Mode Input Voltage Limit | Go |
0x15 | REG0x15_Timer_Control | Timer Control | Go |
0x17 | REG0x17_Charger_Control | Charger Control | Go |
0x18 | REG0x18_Pin_Control | Pin Control | Go |
0x19 | REG0x19_Power_Path_and_Reverse_Mode_Control | Power Path and Reverse Mode Control | Go |
0x1B | REG0x1B_TS_Charging_Threshold_Control | TS Charging Threshold Control | Go |
0x1C | REG0x1C_TS_Charging_Region_Behavior_Control | TS Charging Region Behavior Control | Go |
0x1D | REG0x1D_TS_Reverse_Mode_Threshold_Control | TS Reverse Mode Threshold Control | Go |
0x1E | REG0x1E_Bypass_and_Overload_Control | Bypass and Overload Control | Go |
0x21 | REG0x21_Charger_Status_1 | Charger Status 1 | Go |
0x22 | REG0x22_Charger_Status_2 | Charger Status 2 | Go |
0x23 | REG0x23_Charger_Status_3 | Charger Status 3 | Go |
0x24 | REG0x24_Fault_Status | Fault Status | Go |
0x25 | REG0x25_Charger_Flag_1 | Charger Flag 1 | Go |
0x26 | REG0x26_Charger_Flag_2 | Charger Flag 2 | Go |
0x27 | REG0x27_Fault_Flag | Fault Flag | Go |
0x28 | REG0x28_Charger_Mask_1 | Charger Mask 1 | Go |
0x29 | REG0x29_Charger_Mask_2 | Charger Mask 2 | Go |
0x2A | REG0x2A_Fault_Mask | Fault Mask | Go |
0x2B | REG0x2B_ADC_Control | ADC Control | Go |
0x2C | REG0x2C_ADC_Channel_Control | ADC Channel Control | Go |
0x2D | REG0x2D_IAC_ADC | IAC ADC | Go |
0x2F | REG0x2F_IOUT_ADC | IOUT ADC | Go |
0x31 | REG0x31_VAC_ADC | VAC ADC | Go |
0x33 | REG0x33_VOUT_ADC | VOUT ADC | Go |
0x37 | REG0x37_TS_ADC | TS ADC | Go |
0x3B | REG0x3B_Gate_Driver_Strength_Control | Gate Driver Strength Control | Go |
0x3C | REG0x3C_Gate_Driver_Dead_Time_Control | Gate Driver Dead Time Control | Go |
0x3D | REG0x3D_Part_Information | Part Information | Go |
0x62 | REG0x62_Reverse_Mode_Battery_Discharge_Current | Reverse Mode Battery Discharge Current | Go |
Complex bit access types are encoded to fit into small table cells. Table 7-4 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
REG0x02_Output_Current_Limit is shown in Table 7-5.
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I2C REG0x03=[15:8], I2C REG0x02=[7:0]
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
15:11 | RESERVED | R | 0x0 | Reserved | |
10:2 | IOUT_REG | R/W | 0x190 | Reset by: REG_RESET WATCHDOG | Output Current Regulation Limit with 5mΩ ROUT_SNS: Actual charge current is the lower of IOUT_REG and IOUT pin POR: 20000mA (190h) Range: 400mA-20000mA (8h-190h) Clamped Low Clamped High Bit Step: 50mA |
1:0 | RESERVED | R | 0x0 | Reserved |
REG0x04_Output_Voltage_Limit is shown in Table 7-6.
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I2C REG0x05=[15:8], I2C REG0x04=[7:0]
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
15:14 | RESERVED | R | 0x0 | Reserved | |
13:2 | VOUT_REG | R/W | 0xFA | Reset by: REG_RESET | Output Voltage Regulation Limit: POR: 5000mV
(FAh) Range: 3300mV-26000mV (A5h-514h) Clamped Low Clamped High Bit Step: 20mV |
1:0 | RESERVED | R | 0x0 | Reserved |
REG0x06_Input_Current_DPM_Limit is shown in Table 7-7.
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I2C REG0x07=[15:8], I2C REG0x06=[7:0]
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
15:11 | RESERVED | R | 0x0 | Reserved | |
10:2 | IAC_DPM | R/W | 0x190 | Reset by: REG_RESET | Input Current DPM Regulation Limit with 5mΩ RAC_SNS: Actual input current limit is the lower of IAC_DPM and IIN pin POR: 20000mA (190h) Range: 400mA-20000mA (8h-190h) Clamped Low Clamped High Bit Step: 50mA |
1:0 | RESERVED | R | 0x0 | Reserved |
REG0x08_Input_Voltage_DPM_Limit is shown in Table 7-8.
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I2C REG0x09=[15:8], I2C REG0x08=[7:0]
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
15:14 | RESERVED | R | 0x0 | Reserved | |
13:2 | VAC_DPM | R/W | 0xD2 | Reset by: REG_RESET | Input Voltage Regulation Limit: POR: 4400mV
(DCh) Range: 4400mV-26000mV (DCh-514h) Clamped Low Clamped High Bit Step: 20mV |
1:0 | RESERVED | R | 0x0 | Reserved |
REG0x0A_Reverse_Mode_Input_Current_Limit is shown in Table 7-9.
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I2C REG0x0B=[15:8], I2C REG0x0A=[7:0]
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
15:11 | RESERVED | R | 0x0 | Reserved | |
10:2 | IAC_REV | R/W | 0x190 | Reset by: REG_RESET | Input Current Regulation in Reverse Mode with 5mΩ RAC_SNS:
POR: 20000mA (190h) Range: 400mA-20000mA (8h-190h) Clamped Low Clamped High Bit Step: 50mA |
1:0 | RESERVED | R | 0x0 | Reserved |
REG0x0C_Reverse_Mode_Input_Voltage_Limit is shown in Table 7-10.
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I2C REG0x0D=[15:8], I2C REG0x0C=[7:0]
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
15:14 | RESERVED | R | 0x0 | Reserved | |
13:2 | VAC_REV | R/W | 0xFA | Reset by: REG_RESET | VAC Voltage Regulation in Reverse Mode: POR:
5000mV (FAh) Range: 3300mV-26000mV (A5h-514h) Clamped Low Clamped High Bit Step: 20mV |
1:0 | RESERVED | R | 0x0 | Reserved |
REG0x15_Timer_Control is shown in Table 7-11.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7:6 | RESERVED | R | 0x0 | Reserved | |
5:4 | WATCHDOG | R/W | 0x1 | Reset by: REG_RESET | Watchdog timer control:
00b = Disable 01b = 40s 10b = 80s 11b = 160s |
3 | RESERVED | R | 0x0 | Reserved | |
2:1 | RESERVED | R | 0x0 | Reserved | |
0 | RESERVED | R | 0x0 | Reserved |
REG0x17_Charger_Control is shown in Table 7-12.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7:6 | RESERVED | R | 0x0 | Reserved | |
5 | WD_RST | R/W | 0x0 | Reset by: REG_RESET | I2C Watchdog timer reset control:
0b = Normal 1b = Reset (bit goes back to 0 after timer reset) |
4 | DIS_CE_PIN | R/W | 0x0 | Reset by: REG_RESET | /CE pin function disable:
0b = CE pin enabled 1b = CE pin disabled |
3 | EN_CHG_BIT_RESET_BEHAVIOR | R/W | 0x1 | Reset by: REG_RESET | Controls the EN_CHG bit behavior when WATCHDOG expires:
0b = EN_CHG bit resets to 0 1b = EN_CHG bit resets to 1 |
2 | EN_HIZ | R/W | 0x0 | Reset by: REG_RESET WATCHDOG Adapter Plug In | HIZ mode enable:
0b = Disable 1b = Enable |
1 | EN_IBAT_LOAD | R/W | 0x0 | Sinks current from SRP to GND. Recommend to disable IBAT ADC (IBAT_ADC_DIS = 1)
while this bit is active. Reset by: REG_RESET WATCHDOG | Battery Load (IBAT_LOAD) Enable:
0b = Disabled 1b = Enabled |
0 | EN_CHG | R/W | 0x1 | Reset by: REG_RESET WATCHDOG | Charge enable control:
0b = Disable 1b = Enable |
REG0x18_Pin_Control is shown in Table 7-13.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | EN_IOUT_PIN | R/W | 0x1 | Reset by: REG_RESET WATCHDOG | IOUT pin function enable:
0b = IOUT pin disabled 1b = IOUT pin enabled |
6 | EN_IIN_PIN | R/W | 0x1 | Reset by: REG_RESET WATCHDOG | IIN pin function enable:
0b = IIN pin disabled 1b = IIN pin enabled |
5 | DIS_PG_PIN | R/W | 0x0 | Reset by: REG_RESET | PG pin function disable:
0b = PG pin enabled 1b = PG pin disabled |
4 | DIS_STAT_PIN | R/W | 0x0 | Reset by: REG_RESET | STAT pin function disable:
0b = STAT pin enabled 1b = STAT pin disabled |
3 | FORCE_STAT4_ON | R/W | 0x0 | Reset by: REG_RESET | CE_STAT4 pin override: Can only be forced on if DIS_CE_PIN = 1 0b = CE_STAT4 open-drain off 1b = CE_STAT4 pulls LOW |
2 | FORCE_STAT3_ON | R/W | 0x0 | Reset by: REG_RESET | PG_STAT3 pin override: Can only be forced on if DIS_PG_PIN = 1 0b = PG_STAT3 open-drain off 1b = PG_STAT3 pulls LOW |
1 | RESERVED | R | 0x0 | Reserved | |
0 | FORCE_STAT_ON | R/W | 0x0 | Reset by: REG_RESET | STAT pin override: Can only be forced on if DIS_STAT_PIN = 1 0b = STAT open-drain off 1b = STAT pulls LOW |
REG0x19_Power_Path_and_Reverse_Mode_Control is shown in Table 7-14.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | REG_RST | R/W | 0x0 | Reset by: REG_RESET | Register reset to default values:
0b = Not reset 1b = Reset (bit goes back to 0 after register reset) |
6 | EN_IAC_LOAD | R/W | 0x0 | Reset by: REG_RESET WATCHDOG | VAC Load (IAC_LOAD) Enable:
0b = Disabled 1b = Enabled |
5 | EN_PFM | R/W | 0x0 | It is recommended to disable PFM when ITERM < 2A Reset by: REG_RESET | Enable PFM mode to improve light-load efficiency: Note this bit is reset upon a valid SYNC signal detection on FSW_SYNC pin. Host can set this bit back to 1 to force PFM operation even with a valid SYNC input 0b = Disable (Fixed-frequency DCM operation) 1b = Enable (PFM operation) |
4 | RESERVED | R | 0x0 | Reserved | |
3 | PWRPATH_REDUCE_VDRV | R/W | 0x0 | Reset by: REG_RESET WATCHDOG | Bypass Mode Gate-Drive Voltage Select:
0b = 10V 1b = 7V |
2 | RESERVED | R | 0x0 | Reserved | |
1 | EN_AUTO_REV | R/W | 0x0 | To exit reverse mode, it is recommended to clear both EN_AUTO_REV and EN_REV bits Reset by: REG_RESET WATCHDOG | Auto Reverse Mode to regulate SYS when VBAT < VSYS_REV register:
0b = Disable Auto Reverse 1b = Enable Auto Reverse |
0 | EN_REV | R/W | 0x0 | To exit reverse mode, it is recommended to clear both EN_AUTO_REV and EN_REV bits Reset by: REG_RESET WATCHDOG Adapter Plug In | Reverse Mode control:
0b = Disable 1b = Enable |
REG0x1B_TS_Charging_Threshold_Control is shown in Table 7-15.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7:6 | TS_T5 | R/W | 0x2 | Reset by: REG_RESET | TS T5 (HOT) threshold control:
00b = 41.2% (50C) 01b = 37.7% (55C) 10b = 34.375% (60C) 11b = 31.25%(65C) |
5:4 | RESERVED | R | 0x0 | Reserved | |
3:2 | RESERVED | R | 0x0 | Reserved | |
1:0 | TS_T1 | R/W | 0x2 | Reset by: REG_RESET | TS T1 (COLD) threshold control:
00b = 77.15% (-10C) 01b = 75.32% (-5C) 10b = 73.25% (0C) 11b = 71.1% (5C) |
REG0x1C_TS_Charging_Region_Behavior_Control is shown in Table 7-16.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved | |
6:5 | RESERVED | R | 0x0 | Reserved | |
4 | RESERVED | R | 0x0 | Reserved | |
3:2 | RESERVED | R | 0x0 | Reserved | |
1 | RESERVED | R | 0x0 | Reserved | |
0 | EN_TS | R/W | 0x0 | Reset by: REG_RESET | TS pin function control (applies to forward charging and reverse discharging modes):
0b = Disabled (ignore TS pin) 1b = Enabled |
REG0x1D_TS_Reverse_Mode_Threshold_Control is shown in Table 7-17.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7:6 | BHOT | R/W | 0x1 | Reset by: REG_RESET | Reverse Mode TS HOT temperature threshold control:
00b = 37.7% (55C) 01b = 34.2% (60C) 10b = 31.25%(65C) 11b = Disable |
5 | BCOLD | R/W | 0x0 | Reset by: REG_RESET | Reverse Mode TS COLD temperature threshold control:
0b = 77.15% (-10C) 1b = 80% (-20C) |
4:0 | RESERVED | R | 0x0 | Reserved |
REG0x1E_Bypass_and_Overload_Control is shown in Table 7-18.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | RESERVED | R/W | 0x0 | Reserved | |
6 | TOVLD_SET | R/W | 0x0 | Reset by: REG_RESET | TOVLD timer control:
0b = 25ms 1b = 50ms |
5 | SYSREV_UV | R/W | 0x1 | Reset by: REG_RESET | Reverse Mode System UVP:
0b = 80% of VSYS_REV target 1b = Fixed at 3.3V |
4 | EN_BYPASS | R/W | 0x0 | Bypass mode only supported in forward mode, not operational in reverse mode. Reset by: REG_RESET WATCHDOG | Bypass mode control: Note the device automatically clears this bit and sets EN_HIZ bit when the output current exceeds IOUT_REG register value in bypass mode. 0b = Disable 1b = Enable |
3 | EN_OVLD_TMAX | R/W | 0x0 | Reset by: REG_RESET | TMAX counter control:
0b = Disable TMAX: allows new overload event after tOVLD and current falling below ILIM1 1b = Enable TMAX: allow new overload event after tMAX, even if current does not fall below ILIM1 |
2 | EN_OVLD_3L | R/W | 0x0 | Reset by: REG_RESET | Three-level overload mode control:
0b = Disable 1b = Enable |
1 | OVLD_ILIM2 | R/W | 0x0 | Reset by: REG_RESET | Overload higher current limit (percentage above IIN or IOUT):
0b = 1.5 1b = 2 |
0 | EN_OVLD | R/W | 0x0 | Reset by: REG_RESET | Overload Mode control:
0b = Disable 1b = Enable |
REG0x21_Charger_Status_1 is shown in Table 7-19.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | ADC_DONE_STAT | R | 0x0 | ADC conversion status (in one-shot mode only):
0b = Conversion not complete 1b = Conversion complete | |
6 | IAC_DPM_STAT | R | 0x0 | Input Current regulation status:
0b = Normal 1b = In Input Current regulation (ILIM pin or IAC_DPM) | |
5 | VAC_DPM_STAT | R | 0x0 | Input Voltage regulation status:
0b = Normal 1b = In Input Voltage regulation (VAC_DPM or VSYS_REV) | |
4 | RESERVED | R | 0x0 | Reserved | |
3 | WD_STAT | R | 0x0 | I2C Watchdog timer status:
0b = Normal 1b = WD timer expired | |
2:0 | CHARGE_STAT | R | 0x0 | Charge cycle status: 011 - CC Mode 1xx - CV Mode All others - Reserved 000b = Not charging 001b = Trickle Charge (VBAT < VBAT_SHORT) 010b = Pre-Charge (VBAT < VBAT_LOWV) 011b = Fast Charge (CC mode) 100b = Taper Charge (CV mode) 101b = Float Charge 110b = Top-off Timer Charge 111b = Charge Termination Done |
REG0x22_Charger_Status_2 is shown in Table 7-20.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | PG_STAT | R | 0x0 | Input Power Good status:
0b = Not Power Good 1b = Power Good | |
6:4 | TS_STAT | R | 0x0 | TS (Battery NTC) status:
000b = Normal 001b = TS Warm 010b = TS Cool 011b = TS Cold 100b = TS Hot | |
3:2 | RESERVED | R | 0x0 | Reserved | |
1:0 | RESERVED | R | 0x0 | Reserved |
REG0x23_Charger_Status_3 is shown in Table 7-21.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7:6 | RESERVED | R | 0x0 | Reserved | |
5:4 | FSW_SYNC_STAT | R | 0x0 | FSW_SYNC pin status:
00b = Normal, no external clock detected 01b = Valid ext. clock detected 10b = Pin fault (frequency out-of-range) 11b = Reserved | |
3 | RESERVED | R | 0x0 | Reserved | |
2 | REVERSE_STAT | R | 0x0 | Converter Reverse Mode status:
0b = Reverse Mode off 1b = Reverse Mode On | |
1 | RESERVED | R | 0x0 | Reserved | |
0 | RESERVED | R | 0x0 | Reserved |
REG0x24_Fault_Status is shown in Table 7-22.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | VAC_UV_STAT | R | 0x0 | Input under-voltage status:
0b = Input Normal 1b = Device in Input under-voltage protection | |
6 | VAC_OV_STAT | R | 0x0 | Input over-voltage status:
0b = Input Normal 1b = Device in Input over-voltage protection | |
5 | IBAT_OCP_STAT | R | 0x0 | Battery over-current status:
0b = Battery current normal 1b = Battery over-current detected | |
4 | VBAT_OV_STAT | R | 0x0 | Battery over-voltage status:
0b = Normal 1b = Device in Battery over-voltage protection | |
3 | TSHUT_STAT | R | 0x0 | Thermal shutdown status:
0b = Normal 1b = Device in thermal shutdown protection | |
2 | RESERVED | R | 0x0 | Reserved | |
1 | DRV_OKZ_STAT | R | 0x0 | DRV_SUP pin voltage status:
0b = Normal 1b = DRV_SUP pin voltage is out of valid range | |
0 | RESERVED | R | 0x0 | Reserved |
REG0x25_Charger_Flag_1 is shown in Table 7-23.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | ADC_DONE_FLAG | R | 0x0 | ADC conversion INT flag (in one-shot mode only): Note: always reads 0 in continuous mode Access: R (ClearOnRead) 0b = Conversion not complete 1b = Conversion complete | |
6 | IAC_DPM_FLAG | R | 0x0 | Input Current regulation INT flag:
Access: R (ClearOnRead) 0b = Normal 1b = Device entered Input Current regulation | |
5 | VAC_DPM_FLAG | R | 0x0 | Input Voltage regulation INT flag:
Access: R (ClearOnRead) 0b = Normal 1b = Device entered Input Voltage regulation | |
4 | RESERVED | R | 0x0 | Reserved | |
3 | WD_FLAG | R | 0x0 | I2C Watchdog timer INT flag:
Access: R (ClearOnRead) 0b = Normal 1b = WD_STAT rising edge detected | |
2 | RESERVED | R | 0x0 | Reserved | |
1 | RESERVED | R | 0x0 | Reserved | |
0 | CHARGE_FLAG | R | 0x0 | Charge cycle INT flag:
Access: R (ClearOnRead) 0b = Not charging 1b = CHARGE_STAT[2:0] bits changed (transition to any state) |
REG0x26_Charger_Flag_2 is shown in Table 7-24.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | PG_FLAG | R | 0x0 | Input Power Good INT flag:
Access: R (ClearOnRead) 0b = Normal 1b = PG signal toggle detected | |
6 | RESERVED | R | 0x0 | Reserved | |
5 | RESERVED | R | 0x0 | Reserved | |
4 | TS_FLAG | R | 0x0 | TS (Battery NTC) INT flag:
Access: R (ClearOnRead) 0b = Normal 1b = TS_STAT[2:0] bits changed (transitioned to any state) | |
3 | REVERSE_FLAG | R | 0x0 | Reverse Mode INT flag:
Access: R (ClearOnRead) 0b = Normal 1b = Reverse Mode toggle detected | |
2 | RESERVED | R | 0x0 | Reserved | |
1 | FSW_SYNC_FLAG | R | 0x0 | FSW_SYNC pin signal INT flag:
Access: R (ClearOnRead) 0b = Normal 1b = FSW_SYNC status changed | |
0 | RESERVED | R | 0x0 | Reserved |
REG0x27_Fault_Flag is shown in Table 7-25.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | VAC_UV_FLAG | R | 0x0 | Input under-voltage INT flag:
Access: R (ClearOnRead) 0b = Normal 1b = Entered input under-voltage fault | |
6 | VAC_OV_FLAG | R | 0x0 | Input over-voltage INT flag:
Access: R (ClearOnRead) 0b = Normal 1b = Entered Input over-voltage fault | |
5 | IBAT_OCP_FLAG | R | 0x0 | Battery over-current INT flag:
Access: R (ClearOnRead) 0b = Normal 1b = Entered Battery over-current fault | |
4 | VBAT_OV_FLAG | R | 0x0 | Battery over-voltage INT flag:
Access: R (ClearOnRead) 0b = Normal 1b = Entered battery over-voltage fault | |
3 | TSHUT_FLAG | R | 0x0 | Thermal shutdown INT flag:
Access: R (ClearOnRead) 0b = Normal 1b = Entered TSHUT fault | |
2 | RESERVED | R | 0x0 | Reserved | |
1 | DRV_OKZ_FLAG | R | 0x0 | DRV_SUP pin voltage INT flag:
Access: R (ClearOnRead) 0b = Normal 1b = DRV_SUP pin fault detected | |
0 | RESERVED | R | 0x0 | Reserved |
REG0x28_Charger_Mask_1 is shown in Table 7-26.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | ADC_DONE_MASK | R/W | 0x0 | Reset by: REG_RESET | ADC conversion INT mask (in one-shot mode only):
0b = ADC_DONE produces INT pulse 1b = ADC_DONE does not produce INT pulse |
6 | IAC_DPM_MASK | R/W | 0x0 | Reset by: REG_RESET | Input Current regulation INT mask:
0b = IAC_DPM_FLAG produces INT pulse 1b = IAC_DPM_FLAG does not produce INT pulse |
5 | VAC_DPM_MASK | R/W | 0x0 | Reset by: REG_RESET | Input Voltage regulation INT mask:
0b = VAC_DPM_FLAG produces INT pulse 1b = VAC_DPM_FLAG does not produce INT pulse |
4 | RESERVED | R | 0x0 | Reserved | |
3 | WD_MASK | R/W | 0x0 | Reset by: REG_RESET | I2C Watchdog timer INT mask:
0b = WD expiration produces INT pulse 1b = WD expiration does not produce INT pulse |
2 | RESERVED | R | 0x0 | Reserved | |
1 | RESERVED | R | 0x0 | Reserved | |
0 | CHARGE_MASK | R/W | 0x0 | Reset by: REG_RESET | Charge cycle INT mask:
0b = CHARGE_STAT change produces INT pulse 1b = CHARGE_STAT change does not produces INT pulse |
REG0x29_Charger_Mask_2 is shown in Table 7-27.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | PG_MASK | R/W | 0x0 | Reset by: REG_RESET | Input Power Good INT mask:
0b = PG toggle produces INT pulse 1b = PG toggle does not produce INT pulse |
6 | RESERVED | R | 0x0 | Reserved | |
5 | RESERVED | R | 0x0 | Reserved | |
4 | TS_MASK | R/W | 0x0 | Reset by: REG_RESET | TS (Battery NTC) INT mask:
0b = TS_STAT change produces INT pulse 1b = TS_STAT change does not produce INT pulse |
3 | REVERSE_MASK | R/W | 0x0 | Reset by: REG_RESET | Reverse Mode INT mask:
0b = REVERSE_STAT toggle produces INT pulse 1b = REVERSE_STAT toggle does no produce INT pulse |
2 | RESERVED | R | 0x0 | Reserved | |
1 | FSW_SYNC_MASK | R/W | 0x0 | Reset by: REG_RESET | FSW_SYNC pin signal INT mask:
0b = FSW_SYNC status change produces INT pulse 1b = FSW_SYNC status change does not produce INT pulse |
0 | RESERVED | R/W | 0x0 | Reserved |
REG0x2A_Fault_Mask is shown in Table 7-28.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | VAC_UV_MASK | R/W | 0x0 | Reset by: REG_RESET | Input under-voltage INT mask:
0b = Input under-voltage event produces INT pulse 1b = Input under-voltage event does not produce INT pulse |
6 | VAC_OV_MASK | R/W | 0x0 | Reset by: REG_RESET | Input over-voltage INT mask:
0b = Input over-voltage event produces INT pulse 1b = Input over-voltage event does not produce INT pulse |
5 | IBAT_OCP_MASK | R/W | 0x0 | Reset by: REG_RESET | Battery over-current INT mask:
0b = Battery over-current event produces INT pulse 1b = Battery over-current event does not produce INT pulse |
4 | VBAT_OV_MASK | R/W | 0x0 | Reset by: REG_RESET | Battery over-voltage INT mask:
0b = Battery over-voltage event produces INT pulse 1b = Battery over-voltage event does not produce INT pulse |
3 | TSHUT_MASK | R/W | 0x0 | Reset by: REG_RESET | Thermal shutdown INT mask:
0b = TSHUT event produces INT pulse 1b = TSHUT event does not produce INT pulse |
2 | RESERVED | R | 0x0 | Reserved | |
1 | DRV_OKZ_MASK | R/W | 0x0 | Reset by: REG_RESET | DRV_SUP pin voltage INT mask:
0b = DRV_SUP pin fault produces INT pulse 1b = DRV_SUP pin fault does not produce INT pulse |
0 | RESERVED | R | 0x0 | Reserved |
REG0x2B_ADC_Control is shown in Table 7-29.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | ADC_EN | R/W | 0x0 | When EN_VREG_TEMP_COMP = 1, the ADC will be automatically enabled, regardless of the status of ADC_EN Reset by: REG_RESET WATCHDOG | ADC control:
0b = Disable ADC 1b = Enable ADC |
6 | ADC_RATE | R/W | 0x1 | Reset by: REG_RESET | ADC conversion rate control:
0b = Continuous conversion 1b = One-shot conversion |
5:4 | ADC_SAMPLE | R/W | 0x2 | Reset by: REG_RESET | ADC sample speed:
00b = 15 bit effective resolution 01b = 14 bit effective resolution 10b = 13 bit effective resolution 11b = Reserved |
3 | ADC_AVG | R/W | 0x0 | Reset by: REG_RESET | ADC average control:
0b = Single value 1b = Running average |
2 | ADC_AVG_INIT | R/W | 0x0 | Reset by: REG_RESET | ADC average initial value control:
0b = Start average using existing register value 1b = Start average using new ADC conversion |
1:0 | RESERVED | R | 0x0 | Reserved |
REG0x2C_ADC_Channel_Control is shown in Table 7-30.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7 | IAC_ADC_DIS | R/W | 0x0 | Reset by: REG_RESET | IAC ADC control
0b = Enable 1b = Disable |
6 | IOUT_ADC_DIS | R/W | 0x0 | Recommend to disable IOUT ADC channel when EN_IBAT_LOAD bit is 1 Reset by: REG_RESET | IOUT ADC control
0b = Enable 1b = Disable |
5 | VAC_ADC_DIS | R/W | 0x0 | Reset by: REG_RESET | VAC ADC control
0b = Enable 1b = Disable |
4 | VOUT_ADC_DIS | R/W | 0x0 | Reset by: REG_RESET | VOUT ADC control
0b = Enable 1b = Disable |
3 | RESERVED | R | 0x1 | Reserved | |
2 | TS_ADC_DIS | R/W | 0x0 | Reset by: REG_RESET | TS ADC control
0b = Enable 1b = Disable |
1 | RESERVED | R | 0x1 | Reserved | |
0 | RESERVED | R | 0x0 | Reserved |
REG0x2D_IAC_ADC is shown in Table 7-31.
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I2C REG0x2E=[15:8], I2C REG0x2D=[7:0]
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
15:0 | IAC_ADC | R | 0x0 | IAC ADC reading with 5mΩ RAC_SNS: Reported as 2s complement POR: 0mA(0h) Format: 2s Complement Range: -20000mA - 20000mA (9E58h-61A8h) Clamped Low Clamped High Bit Step: 0.8mA |
REG0x2F_IOUT_ADC is shown in Table 7-32.
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I2C REG0x30=[15:8], I2C REG0x2F=[7:0]
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
15:0 | IOUT_ADC | R | 0x0 | IOUT ADC reading with 5mΩ RBAT_SNS: Reported as 2s complement POR: 0mA (0h) Format: 2s Complement Range: -20000mA-20000mA (D8F0h-2710h) Clamped Low Clamped High Bit Step: 2mA |
REG0x31_VAC_ADC is shown in Table 7-33.
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I2C REG0x32=[15:8], I2C REG0x31=[7:0]
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
15:0 | VAC_ADC | R | 0x0 | VAC ADC reading: Reported as unsigned integer POR: 0mV (0h) Range: 0mV-65534mV (0h-7FFFh) Bit Step: 2mV |
REG0x33_VOUT_ADC is shown in Table 7-34.
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I2C REG0x34=[15:8], I2C REG0x33=[7:0]
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
15:0 | VOUT_ADC | R | 0x0 | VOUT ADC reading: Reported as unsigned integer POR: 0mV (0h) Format: 2s Complement Range: 0mV-65534mV (0h-7FFFh) Clamped Low Bit Step: 2mV |
REG0x37_TS_ADC is shown in Table 7-35.
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I2C REG0x38=[15:8], I2C REG0x37=[7:0]
Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
15:0 | TS_ADC | R | 0x0 | TS ADC reading as percentage of REGN: Reported as unsigned integer POR: 0%(0h) Range: 0% - 99.90234375% (0h-3FFh) Clamped High Bit Step: 0.09765625% |
REG0x3B_Gate_Driver_Strength_Control is shown in Table 7-36.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7:6 | BOOST_HS_DRV | R/W | 0x0 | Reset by: REG_RESET | Boost High Side FET Gate Driver Strength:
00b = Fastest 01b = Faster 10b = Slower 11b = Slowest |
5:4 | BUCK_HS_DRV | R/W | 0x0 | Reset by: REG_RESET | Buck High Side FET Gate Driver Strength:
00b = Fastest 01b = Faster 10b = Slower 11b = Slowest |
3:2 | BOOST_LS_DRV | R/W | 0x0 | Reset by: REG_RESET | Boost Low Side FET Gate Driver Strength:
00b = Fastest 01b = Faster 10b = Slower 11b = Slowest |
1:0 | BUCK_LS_DRV | R/W | 0x0 | Reset by: REG_RESET | Buck Low Side FET Gate Driver Strength:
00b = Fastest 01b = Faster 10b = Slower 11b = Slowest |
REG0x3C_Gate_Driver_Dead_Time_Control is shown in Table 7-37.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7:4 | RESERVED | R | 0x0 | Reserved | |
3:2 | BOOST_DEAD_TIME | R/W | 0x0 | Reset by: REG_RESET | Boost Side FETs Dead Time Control:
00b = 45ns 01b = 75ns 10b = 105ns 11b = 135ns |
1:0 | BUCK_DEAD_TIME | R/W | 0x0 | Reset by: REG_RESET | Buck Side FETs Dead Time Control:
00b = 45ns 01b = 75ns 10b = 105ns 11b = 135ns |
REG0x3D_Part_Information is shown in Table 7-38.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7:6 | RESERVED | R | 0x0 | Reserved | |
5:3 | PART_NUM | R | 0x5 | Part Number: 101 - BQ25758S | |
2:0 | DEV_REV | R | 0x0 | Device Revision: |
REG0x62_Reverse_Mode_Battery_Discharge_Current is shown in Table 7-39.
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Bit | Field | Type | Reset | Notes | Description |
---|---|---|---|---|---|
7:6 | IBAT_REV | R/W | 0x0 | Reset by: REG_RESET | Reverse mode battery discharge current limit:
00b = 20A 01b = 15A 10b = 10A 11b = 5A |
5:2 | RESERVED | R | 0x0 | Reserved | |
1 | EN_CONV_FAST_TRANSIENT | R/W | 0x1 | This bit should be disabled if input or output capacitors are less than 200uF. This bit should be disabled if boost ratio is >2x Reset by: REG_RESET | Enable converter fast transient response -
0b = Disable 1b = Enable |
0 | RESERVED | R/W | 0x0 | Reserved |