SLUSFB0 August 2024 BQ25758S
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The device supports bypass mode to allow VOUT = VAC without regulation and highest efficiency. In this operating mode, the buck and boost high-side FETs (Q1 and Q4) are both turned on, while the Buck and Boost low-side FETs (Q2 and Q3) remain off. The input power is directly passed through the power stage to the output. The switching losses of MOSFETs and the inductor core loss are eliminated, thereby providing highest efficiency. The bypass mode can be enabled by setting the EN_BYPASS register bit to 1.
While device is in bypass mode, the current through ROUT_SNS is monitored and compared against the IOUT_REG register setting. If the output current exceeds the register setting, the device automatically exits bypass mode and enters HIZ mode (completely disabling the power stage). The IBAT_OCP_STAT bit is set, and an INT pulse is asserted to signal the host. To recover from this fault, it is recommended to clear the EN_HIZ bit.