SLUSDG1C June   2020  – August 2022 BQ25792

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Description (continued)
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Device Power-On-Reset
      2. 9.3.2  PROG Pin Configuration
      3. 9.3.3  Device Power Up from Battery without Input Source
      4. 9.3.4  Device Power Up from Input Source
        1. 9.3.4.1 Power Up REGN LDO
        2. 9.3.4.2 Poor Source Qualification
        3. 9.3.4.3 ILIM_HIZ Pin
        4. 9.3.4.4 Default VINDPM Setting
        5. 9.3.4.5 Input Source Type Detection
          1. 9.3.4.5.1 D+/D– Detection Sets Input Current Limit
          2. 9.3.4.5.2 HVDCP Detection Procedure
          3. 9.3.4.5.3 Connector Fault Detection
      5. 9.3.5  Dual-Input Power Mux
        1. 9.3.5.1 ACDRV Turn On Condition
        2. 9.3.5.2 VBUS Input Only
        3. 9.3.5.3 One ACFET-RBFET
        4. 9.3.5.4 Two ACFETs-RBFETs
      6. 9.3.6  Buck-Boost Converter Operation
        1. 9.3.6.1 Force Input Current Limit Detection
        2. 9.3.6.2 Input Current Optimizer (ICO)
        3. 9.3.6.3 Pulse Frequency Modulation (PFM)
        4. 9.3.6.4 Device HIZ State
      7. 9.3.7  USB On-The-Go (OTG)
        1. 9.3.7.1 OTG Mode to Power External Devices
      8. 9.3.8  Power Path Management
        1. 9.3.8.1 Narrow VDC Architecture
        2. 9.3.8.2 Dynamic Power Management
      9. 9.3.9  Battery Charging Management
        1. 9.3.9.1 Autonomous Charging Cycle
        2. 9.3.9.2 Battery Charging Profile
        3. 9.3.9.3 Charging Termination
        4. 9.3.9.4 Charging Safety Timer
        5. 9.3.9.5 Thermistor Qualification
          1. 9.3.9.5.1 JEITA Guideline Compliance in Charge Mode
          2. 9.3.9.5.2 Cold/Hot Temperature Window in OTG Mode
      10. 9.3.10 Integrated 16-Bit ADC for Monitoring
      11. 9.3.11 Status Outputs ( STAT, and INT)
        1. 9.3.11.1 Charging Status Indicator (STAT Pin)
        2. 9.3.11.2 Interrupt to Host ( INT)
      12. 9.3.12 Ship FET Control
        1. 9.3.12.1 Shutdown Mode
        2. 9.3.12.2 Ship Mode
        3. 9.3.12.3 System Power Reset
      13. 9.3.13 Protections
        1. 9.3.13.1 Voltage and Current Monitoring
        2. 9.3.13.2 Thermal Regulation and Thermal Shutdown
      14. 9.3.14 Serial Interface
        1. 9.3.14.1 Data Validity
        2. 9.3.14.2 START and STOP Conditions
        3. 9.3.14.3 Byte Format
        4. 9.3.14.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.3.14.5 Target Address and Data Direction Bit
        6. 9.3.14.6 Single Write and Read
        7. 9.3.14.7 Multi-Write and Multi-Read
    4. 9.4 Device Functional Modes
      1. 9.4.1 Host Mode and Default Mode
      2. 9.4.2 Register Bit Reset
    5. 9.5 Register Map
      1. 9.5.1 I2C Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Input (VBUS / PMID) Capacitor
        3. 10.2.2.3 Output (VSYS) Capacitor
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5 Electrical Characteristics

VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENTS
IQ_BAT_ON Quiescent battery current (BATP, BAT, SYS) when the charger is in the battery only mode, battery FET is enabled, ADC is disabled VBAT = 8V, No VBUS, BATFET is enabled, I2C enabled, ADC disabled, not in ship mode or shut down mode, system is powered by battery. TJ < 85 °C 17 24 µA
IQ_BAT_OFF Quiescent battery current (BATP) for when the charger is in ship mode. VBAT = 8V, No VBUS, I2C enabled, ADC disabled, in ship mode, TJ < 85 °C 11 16 µA
ISD_BAT Shutdown battery current (BATP) when charger is in shut down mode. VBAT = 8V, No VBUS, I2C disabled, ADC disabled, in shut down mode, TJ < 85 °C 0.5 0.7 µA
IQ_BAT_ON Quiescent battery current (BATP, BAT, SYS) when the charger is in the battery only mode, battery FET is enabled, ADC is enabled VBAT = 8V, No VBUS, I2C enabled, ADC enabled, not in ship mode or shut down mode, TJ < 85 °C 540 µA
IQ_VBUS Quiescent input current (VBUS) VBUS = 15V, VBAT = 8V, charge disabled, converter switching, ISYS = 0A, OOA disabled 3 mA
VBUS = 15V, VBAT = 8V, charge disabled, converter switching, ISYS = 0A, OOA enabled 5 mA
ISD_VBUS Shutdown input current (VBUS) in HIZ VBUS = 15V, HIZ mode, no battery, ADC disabled, ACDRV disabled 386 µA
VBUS = 15V, HIZ mode, no battery, ADC disabled, ACDRV enabled 590 µA
IQ_OTG Quiescent battery current (BATP, BAT, SYS) in OTG VBAT = 8V, VBUS = 5V, OTG mode enabled, converter switching, IVBUS = 0A, OOA disabled 3 mA
VBAT = 8V, VBUS = 5V, OTG mode enabled, converter switching, IVBUS = 0A, OOA enabled 5 mA
VBUS / VBAT SUPPLY
VVAC_PRESENT VAC present rising threshold to turn on the ACFET-RBFET For both VAC1 and VAC2 3.4 3.5 V
VAC present falling threshold to turn off the ACFET-RBFET For both VAC1 and VAC2 3.1 3.2 V
VVAC_OVP VAC overvoltage rising threshold, when VAC_OVP[1:0]=00 For both VAC1 and VAC2 25.2 26 26.8 V
VAC overvoltage falling threshold, when VAC_OVP[1:0]=00 For both VAC1 and VAC2 24.4 25.2 26.0 V
VAC overvoltage rising threshold, when VAC_OVP[1:0]=01 For both VAC1 and VAC2 17.4 18.0 18.6 V
VAC overvoltage falling threshold, when VAC_OVP[1:0]=01 For both VAC1 and VAC2 16.9 17.5 18.1 V
VAC overvoltage rising threshold, when VAC_OVP[1:0]=10 For both VAC1 and VAC2 11.6 12 12.4 V
VAC overvoltage falling threshold, when VAC_OVP[1:0]=10 For both VAC1 and VAC2 11.2 11.6 12.0 V
VAC overvoltage rising threshold, when VAC_OVP[1:0]=11 For both VAC1 and VAC2 6.7 7 7.3 V
VAC overvoltage falling threshold, when VAC_OVP[1:0]=11 For both VAC1 and VAC2 6.5 6.8 7.1 V
VVBUS_OP VBUS operating range 3.6 24 V
VVBUS_UVLOZ VBUS rising for active I2C, no battery VBUS rising 3.25 3.4 3.55 V
VVBUS_UVLO VBUS falling to turn off I2C, no battery VBUS falling 3.05 3.2 3.35 V
VVBUS_PRESENT VBUS to start switching VBUS rising 3.3 3.4 3.5 V
VVBUS_PRESENTZ VBUS to stop switching VBUS falling 3.1 3.2 3.3 V
VVBUS_OVP VBUS overvoltage rising threshold VBUS rising 25.2 25.7 26.2 V
VVBUS_OVPZ VBUS overvoltage falling threshold VBUS falling 24.0 24.4 24.8 V
IBUS_OCP IBUS over-current rising threshold 7.0 8.0 9.0 A
IBUS_OCPZ IBUS over-current falling threshold 6.5 7.5 8.5 A
VBAT_UVLOZ BAT voltage for active I2C, no VBUS, no VAC VBAT rising, when the charger is in ship mode 3.25 3.40 3.55 V
VBAT rising, when the charger is in normal mode 2.50 2.60 2.71 V
VBAT_UVLO BAT voltage to turn off I2C, no VBUS, no VAC VBAT falling, when the charger is in ship mode 3.05 3.20 3.31 V
VBAT falling, when the charger is in normal mode 2.30 2.40 2.50 V
VBAT_OTG BAT voltage rising threshold to enable OTG mode VBAT rising 2.7 2.8 2.9 V
VBAT_OTGZ BAT voltage falling threshold to disable OTG mode VBAT falling 2.4 2.5 2.6 V
VPOORSRC Bad adapter detection threshold VBUS falling 3.3 3.4 3.5 V
VPOORSRC Bad adapter detection threshold hysteresis VBUS rising above VPOORSRC 150 200 250 mV
IPOORSRC Bad adapter detection current source 30 mA
RVBUS_PD VBUS pull down resistance 6 kΩ
RVAC_PD VAC pull down resistance For both VAC1 and VAC2 60 Ω
POWER-PATH MANAGEMENT
VSYSMAX_REG_RNG System voltage regulation range, measured on SYS 3.2 19 V
VSYSMAX_REG_ACC System voltage regulation accuracy (when VBAT>VSYSMIN, charging disabled, PFM disabled) VBAT = 16.8V (4s default) 16.82 17.00 17.25 V
VBAT = 12.6V (3s default) 12.62 12.80 13.04 V
VBAT = 8.4V (2s default) 8.44 8.60 8.77 V
VBAT = 4.2V (1s default) 4.268 4.40 4.550 V
VSYSMIN_REG_RNG VSYSMIN regulation range, measured on SYS 2.5 16 V
VSYSMIN_REG_STEP VSYSMIN regulation step size 250 mV
VSYSMIN_REG_ACC 4s battery 11.9 12.2 12.75 V
3s battery 9.0 9.2 9.55 V
2s battery 7.12 7.2 7.52 V
1s battery 3.5 3.7 4.1 V
VSYS_OVP VSYS overvoltage rising threshold As a percentage of the system regulation voltage, to turnoff the converter. 105.5 110.0 112.3 %
VSYS overvoltage rising threshold VSYS_REG = 17V 18.36 18.70 19.04 V
VSYS overvoltage rising threshold VSYS_REG = 8.6V 9.18 9.46 9.67 V
VSYS overvoltage falling threshold As a percentage of the system regulation voltage, to re-enable the converter. 95.5 100 102 %
VSYS overvoltage falling threshold VSYS_REG = 17V 16.66 17 17.34 V
VSYS overvoltage falling threshold VSYS_REG = 8.6V 8.31 8.6 8.78 V
VSYS_SHORT VSYS short voltage falling threshold 2.1 2.2 2.3 V
BATTERY CHARGER
VREG_RANGE Typical charge voltage regulation range 3 18.8 V
VREG_STEP Typical charge voltage step 10 mV
VREG_ACC Charge voltage accuracy, TJ = –40°C - 85°C VREG = 16.8V -0.65 0.55 %
VREG = 12.6V -0.85 0.65 %
VREG = 8.4V -0.25 0.65 %
VREG = 4.2V -0.45 0.95 %
ICHG_RANGE Typical charge current regulation range 0.05 5 A
ICHG_STEP Typical charge current regulation step 10 mA
ICHG_ACC Typical boost mode PWM charge current accuracy, VBUS < VBAT, TJ = –40°C - 85°C ICHG = 2.5A; VBAT=8V -3 7 %
ICHG = 2A; VBAT=8V -2 8 %
ICHG = 1.5A; VBAT=8V 0 10 %
ICHG = 1A; VBAT=8V -2 8 %
ICHG = 0.5A; VBAT=8V -7.5 7.5 %
ICHG_ACC Typical buck mode PWM charge current accuracy, VBUS > VBAT, TJ = –40°C - 85°C ICHG = 4A; VBAT=8V -5.5 2.5 %
ICHG = 2A; VBAT=8V -6.5 3.5 %
ICHG = 1A; VBAT=8V -5 5 %
ICHG = 0.5A; VBAT=8V -7.5 7.5 %
IPRECHG_RANGE Typical pre-charge current range 40 2000 mA
IPRECHG_STEP Typical pre-charge current step 40 mA
IPRECHG_ACC Typical LDO mode charge current accuracy when VBATP below VSYSMIN, VBUS < VBAT, TJ = –40°C - 85°C IPRECHG = 480mA, VBAT = 6.5V -8 8 %
IPRECHG = 200mA, VBAT = 6.5V -20 20 %
IPRECHG = 120mA, VBAT = 6.5V -35 35 %
IPRECHG_ACC Typical LDO mode charge current accuracy when VBATP below VSYSMIN, VBUS > VBAT, TJ = –40°C - 85°C IPRECHG = 1000mA, VBAT = 6.5V -4.5 3.5 %
IPRECHG = 480mA, VBAT = 6.5V -8 8 %
IPRECHG = 200mA, VBAT = 6.5V -20 20 %
IPRECHG = 120mA, VBAT = 6.5V -30 30 %
ITERM_RANGE Typical termination current range 40 1000 mA
ITERM_STEP Typical termination current step 40 mA
ITERM_ACC Termination current accuracy, TJ = –40°C - 85°C ITERM = 120mA, ICHG < 1000mA -20 20 %
ITERM = 480mA, ICHG > 1000mA -14 14 %
VBAT_SHORTZ Battery short voltage rising threshold to start pre-charge VBAT rising 2.25 V
VBAT_SHORT Battery short voltage falling threshold to stop pre-charge VBAT falling 2.06 V
IBAT_SHORT Battery short trickle charging current VBAT < VBAT_SHORTZ 100 mA
VBAT_LOWV_RISE Battery voltage rising threshold to start fast-charge, as percentage of VREG VBAT_LOWV_1:0=00 13 15 17 %
VBAT_LOWV_1:0=01 61.5 63.0 64.5 %
VBAT_LOWV_1:0=10 67.0 68.0 69.0 %
VBAT_LOWV_1:0=11 71.0 72.5 74.0 %
VBAT_LOWV_HYS Battery voltage threshold hysteresis to stop fast-charge on falling edge VBAT falling, as percentage of VREG, VBAT_LOWV_1:0=11 1.4 %
VRECHG Battery recharge threshold VBAT falling, VRECHG=0011, VREG=8.4V 200 mV
VBAT falling, VRECHG=0111, VREG=16.8V 400 mV
IBAT_LOAD Battery discharge load current 30 mA
ISYS_LOAD System discharge load current 30 mA
RBATP BATP Input Resistance 2.5 MΩ
BATFET
VBATFET_FWD BATFET forward voltage in supplement mode BAT discharging current 10mA 30 mV
RBATFET MOSFET on resistance from SYS to BAT 8 mΩ
BATTERY PROTECTIONS
VBAT_OVP Battery overvoltage threshold VBAT rising, as percentage of VREG 103 104 105 %
VBAT rising, VREG = 16.8V 17.30 17.47 17.64 V
VBAT rising, VREG = 8.4V 8.65 8.74 8.82 V
VBAT falling, as percentage of VREG 101 102 103 %
VBAT falling, VREG = 16.8V 16.97 17.14 17.30 V
VBAT falling, VREG = 8.4V 8.48 8.57 8.65 V
VBAT_SHORT Battery short voltage VBAT falling, to clamp the charging current as trickle charging current. 2.06 V
VBAT rising, to release the trickle charging current clamp 2.25 V
IBAT_OCP Battery discharging over-current rising threshold 9.3 A
INPUT VOLTAGE / CURRENT REGULATION
VINDPM_RANGE Typical input voltage regulation range 3.6 22 V
VINDPM_STEP Typical input voltage regulation step 100 mV
VINDPM_ACC Input voltage regulation accuracy VINDPM=18.6V -2 2 %
VINDPM=10.6V -3 3 %
VINDPM=4.3V -5 5 %
IINDPM_RANGE Typical input current regulation range 0.1 3.3 A
IINDPM_STEP Typical input current regulation step 10 mA
IINDPM_ACC Input current regulation accuracy IINDPM = 500mA, VBUS=9V 415 460 500 mA
IINDPM = 1000mA, VBUS=9V 880 940 1000 mA
IINDPM = 2000mA, VBUS=9V 1800 1880 1960 mA
IINDPM = 3000mA, VBUS=9V 2720 2820 2920 mA
VILIM_REG_RNG Voltage range for input current regultion at ILIM_HIZ pin 1 4 V
ILEAK_ILIM ILIM_HIZ pin leakage current VILIM_HIZ = 4V -1.5 1.5 µA
D+ / D- DETECTION
VD+ _600MVSRC D+ voltage source (600 mV) 500 600 700 mV
ID+_10UASRC D+ current source (10 µA) VD+ = 200 mV, 7 10 14 µA
ID+_100UASNK D+ current sink (100 µA) VD+ = 500 mV, 50 90 150 µA
VD+_0P325 D+ comparator threshold for Secondary Detection D+ pin rising, DPDM_NSCOMP2 250 400 mV
VD+_0P8 D+ comparator threshold for Data Contact Detection D+ pin rising, DPDM_NSCOMP2 775 850 925 mV
ID+_LKG Leakage current into D+ HIZ mode -1 1 µA
VD-_600MVSRC D- voltage source (600 mV) 500 600 700 mV
ID-_100UASNK D- current sink (100 µA) VD- = 500 mV, 50 90 150 µA
VD-_0P325 D- comparator threshold for Primary Detection D- pin Rising, DPDM_NSCOMP2 250 400 mV
ID-_LKG Leakage current into D- HIZ mode -1 1 µA
RD-_19K D- resistor to ground (19 kΩ) VD- = 500mV 14.25 24.8 kΩ
VD+ _2p8_hi D+ high comparator threshold for 2.8V detection D+ pin rising, DPDM_NSCOMP2 2.85 3 3.1 V
VD+ _2p8_lo D+ low comparator threshold for 2.8V detection D+ pin rising, NSCMP1Z 2.35 2.45 2.55 V
VD+ _2p8 D+ comparator threshold for non-standard adapter (combined VD+_2p8_hi and VD+_2p8_lo) 2.55 2.85 V
VD- _2p8_hi D- high comparator threshold for 2.8V detection D- pin rising, DPDM_NSCOMP2 2.85 3 3.1 V
VD- _2p8_lo D- low comparator threshold for 2.8V detection D- pin rising, NSCMP1Z 2.35 2.45 2.55 V
VD- _2p8 D- comparator threshold for non-standard adapter (combined VD-_2p8_hi and VD-_2p8_lo) 2.55 2.85 V
VD+ _2p0_hi D+ high comparator threshold for 2.0V detection D+ pin rising, DPDM_NSCOMP2 2.15 2.25 2.35 V
VD+ _2p0_lo D+ low comparator threshold for 2.0V detection D+ pin rising, NSCMP1Z 1.6 1.7 1.85 V
VD+ _2p0 D+ comparator threshold for non-standard adapter (combined VD+_2p0_hi and VD+_2p0_lo) 1.85 2.15 V
VD- _2p0_hi D- high comparator threshold for 2.0V detection D- pin rising, DPDM_NSCOMP2 2.15 2.25 2.35 V
VD- _2p0_lo D- low comparator threshold for 2.0V detection D- pin rising, NSCMP1Z 1.6 1.7 1.85 V
VD- _2p0 D- comparator threshold for non-standard adapter (combined VD-_2p0_hi and VD-_2p0_lo) 1.85 2.15 V
VD+ _1p2_hi D+ high comparator threshold for 1.2V detection D+ pin rising, DPDM_NSCOMP2 1.35 1.5 1.6 V
VD+ _1p2_lo D+ low comparator threshold for 1.2V detection D+ pin rising, NSCPM1Z 0.85 0.95 1.05 V
VD+ _1p2 D+ comparator threshold for non-standard adapter (combined VD+_1p2_hi and VD+_1p2_lo) 1.05 1.35 V
VD- _1p2_hi D- high comparator threshold for 1.2V detection D- pin rising, DPDM_NSCOMP2 1.35 1.5 1.6 V
VD- _1p2_lo D- low comparator threshold for 1.2V detection D- pin rising, NSCMP1Z 0.85 0.95 1.05 V
VD- _1p2 D- comparator threshold for non-standard adapter (combined VD-_1p2_hi and VD-_1p2_lo) 1.05 1.35 V
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG Junction temperature regulation accuracy TREG = 120°C 120 °C
TREG = 100°C 100 °C
TREG = 80°C 80 °C
TREG = 60°C 60 °C
TSHUT Thermal shutdown rising threshold Temperature increasing (TSHUT[1:0]=00) 130 150 170 °C
Temperature increasing (TSHUT[1:0]=01) 110 130 150 °C
Temperature increasing (TSHUT[1:0]=10) 100 120 140 °C
Temperature increasing (TSHUT[1:0]=11) 65 85 105 °C
TSHUT_HYS Thermal shutdown falling hysteresis Temperature decreasing by TSHUT_HYS 30 °C
JEITA THERMISTOR COMPARATOR (CHARGE MODE)
VT1_RISE T1 comparator rising threshold. Charge is suspended above this voltage. As Percentage to REGN (0°C w/ 103AT) 72.4 73.3 74.2 %
VT1_FALL T1 comparator falling threshold. Charge is re-enabled below this voltage. As Percentage to REGN (3°C w/ 103AT) 71.5 72 72.5 %
VT2_RISE T2 comparator rising threshold. As Percentage of REGN, JEITA_T2=5°C w/ 103AT 70.6 71.1 71.6 %
As Percentage of REGN, JEITA_T2=10°C w/ 103AT 67.9 68.4 68.9 %
As Percentage of REGN, JEITA_T2=15°C w/ 103AT 65.0 65.5 66.0 %
As Percentage of REGN, JEITA_T2=20°C w/ 103AT 61.9 62.4 62.9 %
VT2_FALL T2 comparator falling threshold. As Percentage of REGN, JEITA_T2=5°C w/ 103AT 69.3 69.8 70.3 %
As Percentage of REGN, JEITA_T2=10°C w/ 103AT 66.6 67.1 67.6 %
As Percentage of REGN, JEITA_T2=15°C w/ 103AT 63.7 64.2 64.7 %
As Percentage of REGN, JEITA_T2=20°C w/ 103AT 60.6 61.1 61.6 %
VT3_RISE T3 comparator rising threshold. As Percentage of REGN, JEITA_T3=40°C w/ 103AT 49.2 49.7 50.2 %
As Percentage of REGN, JEITA_T3=45°C w/ 103AT 45.6 46.1 46.6 %
As Percentage of REGN, JEITA_T3=50°C w/ 103AT 42.0 42.5 43.0 %
As Percentage of REGN, JEITA_T3=55°C w/ 103AT 38.5 39 39.5 %
VT3_FALL T3 comparator falling threshold. As Percentage of REGN, JEITA_T3=40°C w/ 103AT 47.9 48.4 48.9 %
As Percentage of REGN, JEITA_T3=45°C w/ 103AT 44.3 44.8 45.3 %
As Percentage of REGN, JEITA_T3=50°C w/ 103AT 40.7 41.2 41.7 %
As Percentage of REGN, JEITA_T3=55°C w/ 103AT 37.2 37.7 38.2 %
VT5_FALL T5 comparator falling threshold. Charge is suspended below this voltage. As Percentage of REGN (60°C w/ 103AT) 33.7 34.2 34.7 %
VT5_RISE T5 comparator rising threshold. Charge is re-enabled above this voltage. As Percentage of REGN (58°C w/ 103AT) 35 35.5 36 %
COLD / HOT THERMISTOR COMPARATOR (OTG MODE)
VBCOLD_RISE TCOLD comparator rising threshold. As Percentage of REGN (–20°C w/ 103AT) 79.5 80.0 80.5 %
As Percentage of REGN (–10°C w/ 103AT) 76.6 77.1 77.6 %
VBCOLD_FALL TCOLD comparator falling threshold. As Percentage of REGN (–20°C w/ 103AT) 78.2 78.7 79.2 %
As Percentage of REGN (–10°C w/ 103AT) 75.3 75.8 76.3 %
VBHOT_FALL THOT comparator falling threshold. As Percentage of REGN, (55°C w/ 103AT) 37.2 37.7 38.2 %
As Percentage of REGN, (60°C w/ 103AT) 33.9 34.4 34.9 %
As Percentage of REGN, (65°C w/ 103AT) 30.8 31.3 31.8 %
VBHOT_RISE THOT comparator rising threshold. As Percentage of REGN, (55°C w/ 103AT) 38.8 39.3 39.8 %
As Percentage of REGN, (60°C w/ 103AT) 35.2 35.7 36.2 %
As Percentage of REGN, (65°C w/ 103AT) 32.0 32.5 33.0 %
SWITCHING CONVERTER
FSW PWM switching frequency Oscillator frequency 1.5 MHz
750 kHz
IIN_SS Input current limit during converter start up VSYS below 2.2V, IINDPM above 500mA 500 mA
VBTST_REFRESH Bootstrap refresh comparator threshold VBTST1-VSW1 when Q2 refresh pulse is requested, VBUS = 15V 2.5 3.0 3.6 V
VBTST2-VSW2 when Q3 refresh pulse is requested, VBUS = 15V 2.5 3.0 3.6 V
VF_D Integrated BTST diode forward bias voltage IF=20mA at 25 °C 0.8 V
0.8 V
VR_D Integrated BTST diode reverse breakdown voltage IR=2µA at 25 °C 20 V
20 V
SENSE RESISTANCE and MOSFET Rdson
RSNS VBUS to PMID input sensing resistance Tj = -40°C-85°C (typical value is under 25°C) 6 mΩ
RQ1_ON Buck high-side switching MOSFET turnon resistance between PMID and SW1 Tj = -40°C-85°C (typical value is under 25°C) 24 mΩ
RQ2_ON Buck low-side switching MOSFET turnon resistance between SW1 and PGND Tj = -40°C-85°C (typical value is under 25°C) 35 mΩ
RQ3_ON Boost low-side switching MOSFET turnon resistance between SW2 and PGND Tj = -40°C-85°C (typical value is under 25°C) 28 mΩ
RQ4_ON Boost high-side switching MOSFET turnon resistance between SW2 and SYS Tj = -40°C-85°C (typical value is under 25°C) 17 mΩ
MOSFET CYCLE-BY-CYCLE CURRENT LIMIT
IQ1_CBC Q1 cycle by cycle current limit 7.5 A
IQ2_CBC Q2 cycle by cycle current limit 10 A
IQ3_CBC Q3 cycle by cycle current limit 10 A
IQ4_CBC Q4 cycle by cycle current limit 7.5 A
OTG MODE CONVERTER
VOTG_RANGE Typical OTG mode voltage regulation range 2.8 22 V
VOTG_STEP Typical OTG mode voltage regulation step 10 mV
VOTG_ACC IVBUS = 0A, VOTG = 20V -3.5 3 %
IVBUS = 0A, VOTG = 12V -3.5 3 %
IVBUS = 0A, VOTG = 5V -3.5 3 %
IOTG_RANGE Typical OTG mode current regulation range 0.12 3.32 A
IOTG_STEP Typical OTG mode current regulation step 40 mA
IOTG_ACC OTG mode current regulation accuracy IOTG = 3.0A -2.2 2.2 %
IOTG = 1.52A -5 3 %
IOTG = 0.52A -15 8 %
VOTG_UVP OTG mode under voltage falling threshold 2.1 2.2 2.3 V
VOTG_OVP OTG mode overvoltage rising threshold As percentage of VOTG regulation, OTG mode OOA disabled. 104 113 120 %
OTG mode overvoltage falling threshold As percentage of VOTG regulation 90 98 104 %
IOTG_BAT Battery current regulation in OTG mode IBAT_REG_1:0 = 00, VBAT=8V, VOTG=9V 2.8 3 3.2 A
IBAT_REG_1:0 = 01, VBAT=8V, VOTG=9V 3.8 4 4.2 A
IBAT_REG_1:0 = 10, VBAT=8V, VOTG=9V 4.8 5 5.3 A
REGN LDO
VREGN REGN LDO output voltage VVBUS = 5V, IREGN = 20mA 4.6 4.8 5 V
VVBUS = 15V, IREGN = 20mA 4.8 5 5.2 V
IREGN REGN LDO current limit VVBUS = 5V, VREGN = 4.5V 30 mA
I2C INTERFACE (SCL, SDA)
VIH_SDA Input high threshold level, SDA Pull up rail 1.8V 1.3 V
VIL_SDA Input low threshold level Pull up rail 1.8V 0.4 V
VOL_SDA Output low threshold level Sink current = 5mA 0.4 V
IBIAS_SDA High-level leakage current Pull up rail 1.8V 1 µA
VIH_SCL Input high threshold level, SDA Pull up rail 1.8V 1.3 V
VIL_SCL Input low threshold level Pull up rail 1.8V 0.4 V
VOL_SCL Output low threshold level Sink current = 5mA 0.4 V
IBIAS_SCL High-level leakage current Pull up rail 1.8V 1 µA
LOGIC I PIN (CE, ILIM_HIZ, QON)
VIH_CE Input high threshold level, CE 1.3 V
VIL_CE Input low threshold level, CE 0.4 V
IIN_BIAS_CE High-level leakage current, CE Pull up rail 1.8V 1 µA
VIH_QON Input high threshold level, QON 1.3 V
VIL_QON Input low threshold level, QON 0.4 V
VQON Internal QON pull up QON is pulled up internally 3.2 V
RQON Internal QON pull up resistance 200 kΩ
VIH_ILIM_HIZ Input high threshold level, ILIM_HIZ 1 V
VIL_ILIM_HIZ Input low threshold level, ILIM_HIZ 0.75 V
LOGIC O PIN (INT, STAT)
VOL_INT Output low threshold level, INT Sink current = 5mA 0.4 V
IOUT_BIAS_INT High-level leakage current, INT Pull up rail 1.8V 1 µA
VOL_STAT Output low threshold level, STAT Sink current = 5mA 0.4 V
IOUT_BIAS_STAT High-level leakage current, STAT Pull up rail 1.8V 1 µA
ADC MEASUREMENT ACCURACY AND PERFORMANCE
tADC_CONV Conversion time, each measurement ADC_SAMPLE[1:0] = 00 24 ms
ADC_SAMPLE[1:0] = 01 12 ms
ADC_SAMPLE[1:0] = 10 6 ms
ADC_SAMPLE[1:0] = 11 (Not Recommended) 3 ms
ADCRES Effective resolution ADC_SAMPLE[1:0] = 00 14 15 bits
ADC_SAMPLE[1:0] = 01 13 14 bits
ADC_SAMPLE[1:0] = 10 12 13 bits
ADC_SAMPLE[1:0] = 11 (Not Recommended) 10 11 bits
ADC MEASUREMENT RANGE AND LSB
ADCIBUS_RANGE ADC VBUS current reading range (forward and OTG) Range 0 5 A
ADCIBUS_STEP ADC VBUS current reading step (forward and OTG) LSB 1 mA
ADCVBUS_RANGE ADC VBUS voltage reading range Range 0 30 V
ADCVBUS_STEP ADC VBUS voltage reading step LSB 1 mV
ADCVAC_RANGE ADC VAC voltage reading range Range 0 30 V
ADCVAC_STEP ADC VAC voltage reading step LSB 1 mV
ADCVBAT_RANGE ADC BAT voltage reading range Range 0 20 V
ADCVBAT_STEP ADC BAT voltage reading step LSB 1 mV
ADCVSYS_RANGE ADC SYS voltage reading range Range 0 24 V
ADCVSYS_STEP ADC SYS voltage reading step LSB 1 mV
ADCIBAT_RANGE ADC BAT current reading range Range 0 8 A
ADCIBAT_STEP ADC BAT current reading step LSB 1 mA
ADCTS_RANGE ADC TS voltage reading range Range 0 99.9 %
ADCTS_STEP ADC TS voltage reading step LSB 0.098 %
ADCTDIE_RANGE ADC die temperature reading range Range -40 150 °C
ADCTDIE_STEP ADC die temperature reading step LSB 0.5 °C