SLUSE97
November 2023
BQ76905
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Device Comparison Table
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Supply Current
6.6
Digital I/O
6.7
REGOUT LDO
6.8
Voltage References
6.9
Coulomb Counter
6.10
Coulomb Counter Digital Filter
6.11
Current Wake Detector
6.12
Analog-to-Digital Converter
6.13
Cell Balancing
6.14
Internal Temperature Sensor
6.15
Thermistor Measurement
6.16
Hardware Overtemperature Detector
6.17
Internal Oscillator
6.18
Charge and Discharge FET Drivers
6.19
Comparator-Based Protection Subsystem
6.20
Timing Requirements—I2C Interface, 100-kHz Mode
6.21
Timing Requirements—I2C Interface, 400-kHz Mode
6.22
Timing Diagram
6.23
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Device Configuration
7.3.1
Commands and Subcommands
7.3.2
Configuration Using OTP or Registers
7.3.3
Device Security
7.4
Device Hardware Features
7.4.1
Voltage ADC
7.4.2
Coulomb Counter and Digital Filters
7.4.3
Protection FET Drivers
7.4.4
Voltage References
7.4.5
Multiplexer
7.4.6
LDOs
7.4.7
Standalone Versus Host Interface
7.4.8
ALERT Pin Operation
7.4.9
Low Frequency Oscillator
7.4.10
I2C Serial Communications Interface
7.5
Measurement Subsystem
7.5.1
Voltage Measurement
7.5.1.1
Voltage ADC Scheduling
7.5.1.2
Unused VC Pins
7.5.1.3
General Purpose ADCIN Functionality
7.5.2
Current Measurement and Charge Integration
7.5.3
Internal Temperature Measurement
7.5.4
Thermistor Temperature Measurement
7.5.5
Factory Trim and Calibration
7.6
Protection Subsystem
7.6.1
Protections Overview
7.6.2
Primary Protections
7.6.3
CHG Detector
7.6.4
Cell Open-Wire Protection
7.6.5
Diagnostic Checks
7.7
Cell Balancing
7.8
Device Operational Modes
7.8.1
Overview of Operational Modes
7.8.2
NORMAL Mode
7.8.3
SLEEP Mode
7.8.4
DEEPSLEEP Mode
7.8.5
SHUTDOWN Mode
7.8.6
CONFIG_UPDATE Mode
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Performance Plot
8.2.4
Random Cell Connection Support
8.2.5
Startup Timing
8.2.6
FET Driver Turn-Off
8.2.7
Usage of Unused Pins
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
Support Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RGR|20
MPQF239A
Thermal pad, mechanical data (Package|Pins)
RGR|20
QFND242E
Orderable Information
sluse97_oa
sluse97_pm
1
Features
Battery monitoring capability for 2-series to 5-series cells
Integrated low-side drivers for NFET protection with optional autonomous recovery
Extensive protection suite including voltage, temperature, current, and internal diagnostics
16-bit delta-sigma voltage ADC
High-accuracy cell voltage measurement of 4 mV (typical)
A dedicated simultaneous 16- and 24-bit delta-sigma coulomb counter ADC
High-accuracy current measurement with low input offset error
Wide-range current applications (±200-mV measurement range across sense resistor)
48-bit accumulated charge integrator with timer
Host-controlled cell balancing
Multiple power modes (typical battery pack operating range conditions)
NORMAL mode: 32 μA to 175 μA
SLEEP mode: 6 μA
DEEPSLEEP mode: 2.7 μA
SHUTDOWN Mode: <1 μA
High voltage tolerance of 45 V on cell connect and select additional pins
Support for temperature sensing using an internal sensor and external thermistor
Integrated one-time-programmable (OTP) memory for device settings, programmed by TI
400-kHz I
2
C serial communications with optional CRC support
Programmable LDO for external system usage
20-pin QFN (RGR) package