SLUSE81E August 2020 – November 2023 BQ79612-Q1 , BQ79614-Q1 , BQ79616-Q1 , BQ79616H-Q1
PRODUCTION DATA
BQ79612-Q1, BQ79614-Q1, BQ79616-Q1 and BQ79616H-Q1 provide high-accuracy cell voltage measurements in less than 200 μs for 12S, 14S and 16S battery modules in high-voltage battery management systems in HEV/EV. The family of monitors offers different channel options in the same package type, providing pin-to-pin compatibility and supporting high reuse of the established software and hardware across any platform. The integrated front-end filters enable the system to implement with simple, low voltage rating, differential RC filters on the cell input channels. The integrated, post-ADC, low-pass filters enable filtered, DC-like, voltage measurements for better state of charge (SOC) calculation. This device supports autonomous internal cell balancing with temperature monitoring to auto-pause and resume balancing to avoid an overtemperature condition.
PART NUMBER(1) | PACKAGE | BODY SIZE (NOM) |
---|---|---|
BQ79612-Q1 | HTQFP (64-pin) | 10.00 mm × 10.00 mm |
BQ79614-Q1 | ||
BQ79616-Q1 | ||
BQ79616H-Q1 |
Changes from Revision D (September 2022) to Revision E (November 2023)
Changes from Revision C (June 2021) to Revision D (September 2022)
Changes from Revision B (April 2021) to Revision C (June 2021)
Changes from Revision A (December 2020) to Revision B (April 2021)
Changes from Revision * (August 2020) to Revision A (December 2020)
The inclusion of the isolated, bidirectional, daisy chain ports supports both capacitor- and transformer-based isolation, allowing the use of the most effective components for centralized or distribution architectures commonly found in the xEV powertrain system. This device also includes eight GPIOs or auxiliary inputs that can be used for external thermistor measurements.
Host communication to the BQ7961x-Q1 family of devices can be connected via the device's dedicated UART interface or through a communication bridge device, BQ79600. Additionally, an isolated, differential daisy-chain communication interface allows the host to communicate with the entire battery stack over a single interface. in the event of a communication line break, the daisy-chain communication interface is configurable to a ring architecture that allows the host to talk to devices at either end of the stack.
All references to the BQ79616-Q1 device also apply to the BQ79616H-Q1 device.
DEVICE | STATUS | DESCRIPTION |
---|---|---|
BQ79616-Q1 | Production Data | Supports 6S to 16S battery modules |
BQ79616H-Q1 | Production Data | Supports 6S to 16S battery modules |
BQ79614-Q1 | Production Data | Supports 6S to 14S battery modules |
BQ79612-Q1 | Production Data | Supports 6S to 12S battery modules |
PIN | TYPE | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | No. | ||||
BQ79616/H | BQ79614 | BQ79612 | |||
BAT | BAT | BAT | 1 | P | Power supply input and top of module measurement input. Connect to the top cell of the battery module. |
NPNB | NPNB | NPNB | 48 | P | Connect to the base of an external NPN transistor. |
LDOIN | LDOIN | LDOIN | 47 | P | 6-V preregulated analog power supply input/sense pin. Connect to the emitter of the external NPN transistor and connect a 0.1-µF decoupling capacitor to CVSS. |
AVDD | AVDD | AVDD | 38 | P | 5-V regulated output. AVDD supplies the internal analog circuits. Bypass AVDD with a capacitor to AVSS. |
AVSS | AVSS | AVSS | 39 | GND | Analog ground. Ground connection for internal analog circuits. Connect DVSS, CVSS, REFHM, and AVSS externally. |
NEG5V | NEG5V | NEG5V | 44 | P | Negative 5-V charge pump used for daisy chain and Main ADC. Connect with a capacitor to CVSS. |
DVDD | DVDD | DVDD | 49 | P | 1.8-V regulated output. DVDD supplies the internal digital circuits. Bypass DVDD with a capacitor to DVSS. |
DVSS | DVSS | DVSS | 50 | GND | Digital ground. Ground connection for internal digital logics. Connect DVSS, CVSS, REFHM, and AVSS externally. |
CVDD | CVDD | CVDD | 45 | P | 5-V daisy chain communication and I/Os power supply. CVDD supplies the stack daisy chain communication transceiver circuit and the I/O pins. This power supply also supports an additional 10-mA external load in ACTIVE and SLEEP. |
CVSS | CVSS | CVSS | 46 | GND | Daisy chain communication ground. Ground connection for internal daisy chain transceivers. Connect DVSS, CVSS, REFHM, and AVSS externally. |
TSREF | TSREF | TSREF | 51 | P | 5-V bias voltage for NTC thermistor. Connect TSREF to the top of the NTC resistor divider network to the GPIOs when they are configured for NTC temperature monitoring. Bypass TSREF with a capacitor to CVSS. |
REFHP | REFHP | REFHP | 37 | P | Precision reference output pin. Bypass with a capacitor to REFHM. |
REFHM | REFHM | REFHM | 36 | GND | Precision reference ground. Ground connection for the internal precision reference. Connect DVSS, CVSS, REFHM, and AVSS externally. |
VC16 | NC | NC | 3 | I | Cell voltage sense input. Connect to the positive terminal of cell 16. Connect a differential RC filter to VC15. Tie unused NC pins in BQ79614 and BQ79612 to BAT pin as explained in Cell Connections. |
VC15 | NC | NC | 5 | I | Cell voltage sense input. Connect to the positive terminal of cell 15. Connect a differential RC filter to VC14.Tie unused NC pins in BQ79614 and BQ79612 to BAT pin as explained in Cell Connections. |
VC14 | VC14 | NC | 7 | I | Cell voltage sense input. Connect to the positive terminal of cell 14. Connect a differential RC filter to VC13.Tie unused NC pins in BQ79612 to BAT pin as explained in Cell Connections. |
VC13 | VC13 | NC | 9 | I | Cell voltage sense input. Connect to the positive terminal of cell 13. Connect a differential RC filter to VC12. Tie unused NC pins in BQ79612 to BAT pin as explained in Cell Connections. |
VC12 | VC12 | VC12 | 11 | I | Cell voltage sense input. Connect to the positive terminal of cell 12. Connect a differential RC filter to VC11. |
VC11 | VC11 | VC11 | 13 | I | Cell voltage sense input. Connect to the positive terminal of cell 11. Connect a differential RC filter to VC10. |
VC10 | VC10 | VC10 | 15 | I | Cell voltage sense input. Connect to the positive terminal of cell 10. Connect a differential RC filter to VC9. |
VC9 | VC9 | VC9 | 17 | I | Cell voltage sense input. Connect to the positive terminal of cell 9. Connect a differential RC filter to VC8. |
VC8 | VC8 | VC8 | 19 | I | Cell voltage sense input. Connect to the positive terminal of cell 8. Connect a differential RC filter to VC7. |
VC7 | VC7 | VC7 | 21 | I | Cell voltage sense input. Connect to the positive terminal of cell 7. Connect a differential RC filter to VC6. |
VC6 | VC6 | VC6 | 23 | I | Cell voltage sense input. Connect to the positive terminal of cell 6. Connect a differential RC filter to VC5. |
VC5 | VC5 | VC5 | 25 | I | Cell voltage sense input. Connect to the positive terminal of cell 5. Connect a differential RC filter to VC4. |
VC4 | VC4 | VC4 | 27 | I | Cell voltage sense input. Connect to the positive terminal of cell 4. Connect a differential RC filter to VC3. |
VC3 | VC3 | VC3 | 29 | I | Cell voltage sense input. Connect to the positive terminal of cell 3. Connect a differential RC filter to VC2. |
VC2 | VC2 | VC2 | 31 | I | Cell voltage sense input. Connect to the positive terminal of cell 2. Connect a differential RC filter to VC1. |
VC1 | VC1 | VC1 | 33 | I | Cell voltage sense input. Connect to the positive terminal of cell 1. Connect a differential RC filter to VC0. |
VC0 | VC0 | VC0 | 35 | I | Cell voltage sense input. Connect to the negative terminal of cell 1. Connect a differential RC filter to AVSS. |
CB16 | NC | NC | 2 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 16 with a differential RC filter to CB15. The filter resistor also sets the internal balance current. Tie unused CB16 pin via RC to BAT pin and tie unused NC pins in BQ79614 and BQ79612 to BAT pin as explained in Cell Connections. |
CB15 | NC | NC | 4 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 15 with a differential RC filter to CB14. The filter resistor also sets the internal balance current. Tie unused NC pins in BQ79614 and BQ79612 to BAT pin as explained in Cell Connections. |
CB14 | CB14 | NC | 6 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 14 with a differential RC filter to CB13. The filter resistor also sets the internal balance current. Tie unused NC pins in BQ79612 to BAT pin as explained in Cell Connections. |
CB13 | CB13 | NC | 8 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 13 with a differential RC filter to CB12. The filter resistor also sets the internal balance current. Tie unused NC pins in BQ79612 to BAT pin as explained in Cell Connections. |
CB12 | CB12 | CB12 | 10 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 12 with a differential RC filter to CB11. The filter resistor also sets the internal balance current. |
CB11 | CB11 | CB11 | 12 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 11 with a differential RC filter to CB10. The filter resistor also sets the internal balance current. |
CB10 | CB10 | CB10 | 14 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 10 with a differential RC filter to CB9. The filter resistor also sets the internal balance current. |
CB9 | CB9 | CB9 | 16 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 9 with a differential RC filter to CB8. The filter resistor also sets the internal balance current. |
CB8 | CB8 | CB8 | 18 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 8 with a differential RC filter to CB7. The filter resistor also sets the internal balance current. |
CB7 | CB7 | CB7 | 20 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 7 with a differential RC filter to CB6. The filter resistor also sets the internal balance current. |
CB6 | CB6 | CB6 | 22 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 6 with a differential RC filter to CB5. The filter resistor also sets the internal balance current. |
CB5 | CB5 | CB5 | 24 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 5 with a differential RC filter to CB4. The filter resistor also sets the internal balance current. |
CB4 | CB4 | CB4 | 26 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 4 with a differential RC filter to CB3. The filter resistor also sets the internal balance current. |
CB3 | CB3 | CB3 | 28 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 3 with a differential RC filter to CB2. The filter resistor also sets the internal balance current. |
CB2 | CB2 | CB2 | 30 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 2 with a differential RC filter to CB1. The filter resistor also sets the internal balance current. |
CB1 | CB1 | CB1 | 32 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect this pin to the positive terminal of cell 1 with a differential RC filter to CB0. The filter resistor also sets the internal balance current. |
CB0 | CB0 | CB0 | 34 | I/O | Cell balance connection. This pin is connected to the internal cell balancing FET. Connect to the negative terminal of cell 1 with differential RC filter to AVSS. The filter resistor also sets the internal balance current. |
BBP | BBP | BBP | 64 | I | Bus bar connection. With BBP and BBN connecting to each end of a bus bar, this channel provides a differential input to the ADC measurement with a 5x gain. |
BBN | BBN | BBN | 63 | I | Bus bar connection. With BBP and BBN connecting to each end of a bus bar, this channel provides a differential input to the ADC measurement with a 5x gain. |
RX | RX | RX | 52 | I | UART receiver input. Pull up to CVDD with an external resistor and connect the device RX to the TX output of the host MCU. If unused (for example, for stack devices), connect RX to CVDD. |
TX | TX | TX | 53 | O | UART transmitter output. Connect device TX to RX input of the host MCU and will be pulled up from the host side. If unused (for example, for stack devices), leave it floating. |
COMHP | COMHP | COMHP | 43 | I/O | Vertical bidirectional communication interface for daisy chain connection. High side (north side) differential I/O. Will connect to the low side (south side) COMLP and COMLN of the lower adjacent device in the daisy chain configuration. If unused, connect COMHP and COMHN with a 1kΩ resistor. |
COMHN | COMHN | COMHN | 42 | I/O | |
COMLP | COMLP | COMLP | 40 | I/O | Vertical bidirectional communication interface for daisy chain connection. Low side (south side) differential I/O. Will connect to the high side (north side) COMHP and COMHN of the upper adjacent device in the daisy chain configuration. If unused, connect COMLP and COMLN with a 1kΩ resistor. |
COMLN | COMLN | COMLN | 41 | I/O | |
NFAULT | NFAULT | NFAULT | 62 | O | Fault indication output. Active low. If used on the base device, pull up NFAULT to CVDD with a pullup resistor and connect NFAULT to host MCU GPIO. If unused, leave it unconnected. |
GPIO1 | GPIO1 | GPIO1 | 61 | I/O | General purpose input/output, configuration options are:
|
GPIO2 | GPIO2 | GPIO2 | 60 | I/O | |
GPIO3 | GPIO3 | GPIO3 | 59 | I/O | |
GPIO4 | GPIO4 | GPIO4 | 58 | I/O | |
GPIO5 | GPIO5 | GPIO5 | 57 | I/O | |
GPIO6 | GPIO6 | GPIO6 | 56 | I/O | |
GPIO7 | GPIO7 | GPIO7 | 55 | I/O | |
GPIO8 | GPIO8 | GPIO8 | 54 | I/O |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input Voltage | BAT, VC* (except VC0), CB* (except CB0), NFAULT, BBP, BBN to AVSS (2) (3) | –0.3 | 100 | V |
CB0, VC0 to AVSS | –0.3 | 5.5 | V | |
VCn to VCn-1, n = 1 to 16 (2) | –80 | 80 | V | |
CBn to CBn-1, n = 1 to 16 (3) | –0.3 | 16 | V | |
BBP to BBN | –80 | 80 | V | |
LDOIN to AVSS | –0.3 | 9 | V | |
NPNB to AVSS | –0.3 | 10 | V | |
AVDD to AVSS | –0.3 | 5.5 | V | |
DVDD to DVSS | –0.3 | 1.98 | V | |
CVDD to CVSS | –0.3 | 6 | V | |
TSREF to AVSS | –0.3 | 5.5 | V | |
REFHP to REFHM | –0.3 | 5.5 | V | |
NEG5V to AVSS | –5.5 | 0 | V | |
TX, RX to AVSS | –0.3 | 6 | V | |
COMHP, COMHN, COMLP, COMLN to CVSS | –20 | 20 | V | |
COMHP to COMHN, COMLP to COMLN | –5.5 | 5.5 | V | |
GPIO* to AVSS | –0.3 | 5.5 | V | |
CB* current | Max of 8 cell in balancing at 75oC ambient | 240 | mA | |
I/O current | GPIO*, RX, TX current | 10 | mA | |
TOTP_PROG | Device will not start OTP programming above this temperature | 55 | °C | |
TA | Ambient temperature | –40 | 130 | °C |
TJ | Junction temperature | –40 | 150 | °C |
Tstg | Storage temperature | –65 | 150 | °C |