SLUSE81E August   2020  – November 2023 BQ79612-Q1 , BQ79614-Q1 , BQ79616-Q1 , BQ79616H-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Device Comparison Table
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Supplies
        1. 9.3.1.1 AVAO_REF and AVDD_REF
        2. 9.3.1.2 LDOIN
        3. 9.3.1.3 AVDD
        4. 9.3.1.4 DVDD
        5. 9.3.1.5 CVDD and NEG5V
        6. 9.3.1.6 TSREF
      2. 9.3.2 Measurement System
        1. 9.3.2.1 Main ADC
          1. 9.3.2.1.1 Cell Voltage Measurements
            1. 9.3.2.1.1.1 Analog Front End
            2. 9.3.2.1.1.2 VC Channel Measurements
            3. 9.3.2.1.1.3 Post-ADC Digital LPF
            4. 9.3.2.1.1.4 BBP and BBN Measurements
          2. 9.3.2.1.2 Temperature Measurements
            1. 9.3.2.1.2.1 DieTemp1 Measurement
            2. 9.3.2.1.2.2 GPIOs and TSREF Measurements
          3. 9.3.2.1.3 Main ADC Operation Control
            1. 9.3.2.1.3.1 Operation Modes and Status
        2. 9.3.2.2 AUX ADC
          1. 9.3.2.2.1 AUX Cell Voltage Measurements
            1. 9.3.2.2.1.1 AUX Analog Front End
            2. 9.3.2.2.1.2 CB and BB Channel Measurements
          2. 9.3.2.2.2 AUX Temperature Measurements
            1. 9.3.2.2.2.1 DieTemp2 Measurement
            2. 9.3.2.2.2.2 AUX GPIO Measurements
          3. 9.3.2.2.3 MISC Measurements
          4. 9.3.2.2.4 AUX ADC Operation Control
        3. 9.3.2.3 Synchronization between MAIN and AUX ADC Measurements
      3. 9.3.3 Cell Balancing
        1. 9.3.3.1 Set Up Cell Balancing
          1. 9.3.3.1.1 Step 1: Determine Balancing Channels
          2. 9.3.3.1.2 Step 2: Select Balancing Control Methods
          3. 9.3.3.1.3 Step 3a: Balancing Thermal Management
          4. 9.3.3.1.4 Step 3b: Option to Stop On Cell Voltage Threshold
          5. 9.3.3.1.5 Step 3c: Option to Stop at Fault
        2. 9.3.3.2 Cell Balancing in SLEEP Mode
        3. 9.3.3.3 Pause and Stop Cell Balancing
          1. 9.3.3.3.1 Cell Balancing Pause
          2. 9.3.3.3.2 Cell Balancing Stop
          3. 9.3.3.3.3 Remaining CB Time
        4. 9.3.3.4 Module Balancing
          1. 9.3.3.4.1 Start Module Balancing
          2. 9.3.3.4.2 Stop Module Balancing
      4. 9.3.4 Integrated Hardware Protectors
        1. 9.3.4.1 OVUV Protectors
          1. 9.3.4.1.1 OVUV Operation Modes
          2. 9.3.4.1.2 OVUV Control and Status
            1. 9.3.4.1.2.1 OVUV Control
            2. 9.3.4.1.2.2 OVUV Status
        2. 9.3.4.2 OTUT Protector
          1. 9.3.4.2.1 OTUT Operation Modes
          2. 9.3.4.2.2 OTUT Control and Status
            1. 9.3.4.2.2.1 OTUT Control
            2. 9.3.4.2.2.2 OTUT Status
      5. 9.3.5 GPIO Configuration
      6. 9.3.6 Communication, OTP, Diagnostic Control
        1. 9.3.6.1 Communication
          1. 9.3.6.1.1 Serial Interface
            1. 9.3.6.1.1.1 UART Physical Layer
              1. 9.3.6.1.1.1.1 UART Transmitter
              2. 9.3.6.1.1.1.2 UART Receiver
              3. 9.3.6.1.1.1.3 COMM CLEAR
            2. 9.3.6.1.1.2 Command and Response Protocol
              1. 9.3.6.1.1.2.1 Transaction Frame Structure
                1. 9.3.6.1.1.2.1.1 Frame Initialization Byte
                2. 9.3.6.1.1.2.1.2 Device Address Byte
                3. 9.3.6.1.1.2.1.3 Register Address Bytes
                4. 9.3.6.1.1.2.1.4 Data Bytes
                5. 9.3.6.1.1.2.1.5 CRC Bytes
                6. 9.3.6.1.1.2.1.6 Calculating Frame CRC Value
                7. 9.3.6.1.1.2.1.7 Verifying Frame CRC
              2. 9.3.6.1.1.2.2 Transaction Frame Examples
                1. 9.3.6.1.1.2.2.1 Single Device Read/Write
                2. 9.3.6.1.1.2.2.2 Stack Read/Write
                3. 9.3.6.1.1.2.2.3 Broadcast Read/Write
                4. 9.3.6.1.1.2.2.4 Broadcast Write Reverse Direction
          2. 9.3.6.1.2 Daisy Chain Interface
            1. 9.3.6.1.2.1 Daisy Chain Transmitter and Receiver Functionality
            2. 9.3.6.1.2.2 Daisy Chain Protocol
          3. 9.3.6.1.3 Start Communication
            1. 9.3.6.1.3.1 Identify Base and Stack
            2. 9.3.6.1.3.2 Auto-Addressing
              1. 9.3.6.1.3.2.1 Setting Up the Device Addresses
              2. 9.3.6.1.3.2.2 Setting Up COMM_CTRL[STACK_DEV] and [TOP_STACK]
              3. 9.3.6.1.3.2.3 Storing Device Address to OTP
            3. 9.3.6.1.3.3 Synchronize Daisy Chain DLL
            4. 9.3.6.1.3.4 Ring Communication
          4. 9.3.6.1.4 Communication Timeout
            1. 9.3.6.1.4.1 Short Communication Timeout
            2. 9.3.6.1.4.2 Long Communication Timeout
          5. 9.3.6.1.5 Communication Debug Mode
          6. 9.3.6.1.6 Multidrop Configuration
          7. 9.3.6.1.7 SPI Master
          8. 9.3.6.1.8 SPI Loopback
        2. 9.3.6.2 Fault Handling
          1. 9.3.6.2.1 Fault Status Hierarchy
            1. 9.3.6.2.1.1 Debug Registers
          2. 9.3.6.2.2 Fault Masking and Reset
            1. 9.3.6.2.2.1 Fault Masking
            2. 9.3.6.2.2.2 Fault Reset
          3. 9.3.6.2.3 Fault Signaling
            1. 9.3.6.2.3.1 Fault Status Transmitting in ACTIVE Mode
            2. 9.3.6.2.3.2 Fault Status Transmitting in SLEEP Mode
            3. 9.3.6.2.3.3 Heartbeat and Fault Tone
        3. 9.3.6.3 Nonvolatile Memory
          1. 9.3.6.3.1 OTP Page Status
          2. 9.3.6.3.2 OTP Programming
        4. 9.3.6.4 Diagnostic Control/Status
          1. 9.3.6.4.1 Power Supplies Check
            1. 9.3.6.4.1.1 Power Supply Diagnostic Check
            2. 9.3.6.4.1.2 Power Supply BIST
          2. 9.3.6.4.2 Thermal Shutdown and Warning Check
            1. 9.3.6.4.2.1 Thermal Shutdown
            2. 9.3.6.4.2.2 Thermal Warning
          3. 9.3.6.4.3 Oscillators Watchdog
          4. 9.3.6.4.4 OTP Error Check
            1. 9.3.6.4.4.1 OTP CRC Test and Faults
            2. 9.3.6.4.4.2 OTP Margin Read
            3. 9.3.6.4.4.3 Error Check and Correct (ECC) OTP
          5. 9.3.6.4.5 Integrated Hardware Protector Check
            1. 9.3.6.4.5.1 Parity Check
            2. 9.3.6.4.5.2 OVUV and OTUT DAC Check
            3. 9.3.6.4.5.3 OVUV Protector BIST
            4. 9.3.6.4.5.4 OTUT Protector BIST
          6. 9.3.6.4.6 Diagnostic Through ADC Comparison
            1. 9.3.6.4.6.1 Cell Voltage Measurement Check
            2. 9.3.6.4.6.2 Temperature Measurement Check
            3. 9.3.6.4.6.3 Cell Balancing FETs Check
            4. 9.3.6.4.6.4 VC and CB Open Wire Check
      7. 9.3.7 Bus Bar Support
        1. 9.3.7.1 Bus Bar on BBP/BBN Pins
          1. 9.3.7.1.1 Typical Connection
          2. 9.3.7.1.2 Bus Bar Measurement
          3. 9.3.7.1.3 Cell Balancing Handling
          4. 9.3.7.1.4 Cell Voltage Diagnostic Control
        2. 9.3.7.2 Bus Bar on Individual VC Channel
          1. 9.3.7.2.1 Typical Connection
          2. 9.3.7.2.2 Bus Bar Measurement
          3. 9.3.7.2.3 Cell Balancing Handling
          4. 9.3.7.2.4 Cell Voltage Diagnostic Control
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Modes
        1. 9.4.1.1 SHUTDOWN Mode
          1. 9.4.1.1.1 Exit SHUTDOWN Mode
          2. 9.4.1.1.2 Enter SHUTDOWN Mode
        2. 9.4.1.2 SLEEP Mode
          1. 9.4.1.2.1 Exit SLEEP Mode
          2. 9.4.1.2.2 Enter SLEEP Mode
        3. 9.4.1.3 ACTIVE Mode
          1. 9.4.1.3.1 Exit ACTIVE Mode
          2. 9.4.1.3.2 Enter ACTIVE Mode From SHUTDOWN Mode
          3. 9.4.1.3.3 Enter ACTIVE Mode From SLEEP Mode
      2. 9.4.2 Device Reset
      3. 9.4.3 Ping and Tone
        1. 9.4.3.1 Ping
        2. 9.4.3.2 Tone
        3. 9.4.3.3 Ping and Tone Propagation
    5. 9.5 Register Maps
      1. 9.5.1 OTP Shadow Register Summary
      2. 9.5.2 Read/Write Register Summary
      3. 9.5.3 Read-Only Register Summary
      4. 9.5.4 Register Field Descriptions
        1. 9.5.4.1  Device Addressing Setup
          1. 9.5.4.1.1 DIR0_ADDR_OTP
          2. 9.5.4.1.2 DIR1_ADDR_OTP
          3. 9.5.4.1.3 CUST_MISC1 through CUST_MISC8
          4. 9.5.4.1.4 DIR0_ADDR
          5. 9.5.4.1.5 DIR1_ADDR
        2. 9.5.4.2  Device ID and Scratch Pad
          1. 9.5.4.2.1 PARTID
          2. 9.5.4.2.2 DEV_REVID
          3. 9.5.4.2.3 DIE_ID1 through DIE_ID9
        3. 9.5.4.3  General Configuration and Control
          1. 9.5.4.3.1  DEV_CONF
          2. 9.5.4.3.2  ACTIVE_CELL
          3. 9.5.4.3.3  BBVC_POSN1
          4. 9.5.4.3.4  BBVC_POSN2
          5. 9.5.4.3.5  PWR_TRANSIT_CONF
          6. 9.5.4.3.6  COMM_TIMEOUT_CONF
          7. 9.5.4.3.7  TX_HOLD_OFF
          8. 9.5.4.3.8  STACK_RESPONSE
          9. 9.5.4.3.9  BBP_LOC
          10. 9.5.4.3.10 COMM_CTRL
          11. 9.5.4.3.11 CONTROL1
          12. 9.5.4.3.12 CONTROL2
          13. 9.5.4.3.13 CUST_CRC_HI
          14. 9.5.4.3.14 CUST_CRC_LO
          15. 9.5.4.3.15 CUST_CRC_RSLT_HI
          16. 9.5.4.3.16 CUST_CRC_RSLT_LO
        4. 9.5.4.4  Operation Status
          1. 9.5.4.4.1 DIAG_STAT
          2. 9.5.4.4.2 ADC_STAT1
          3. 9.5.4.4.3 ADC_STAT2
          4. 9.5.4.4.4 GPIO_STAT
          5. 9.5.4.4.5 BAL_STAT
          6. 9.5.4.4.6 DEV_STAT
        5. 9.5.4.5  ADC Configuration and Control
          1. 9.5.4.5.1 ADC_CONF1
          2. 9.5.4.5.2 ADC_CONF2
          3. 9.5.4.5.3 MAIN_ADC_CAL1
          4. 9.5.4.5.4 MAIN_ADC_CAL2
          5. 9.5.4.5.5 AUX_ADC_CAL1
          6. 9.5.4.5.6 AUX_ADC_CAL2
          7. 9.5.4.5.7 ADC_CTRL1
          8. 9.5.4.5.8 ADC_CTRL2
          9. 9.5.4.5.9 ADC_CTRL3
        6. 9.5.4.6  ADC Measurement Results
          1. 9.5.4.6.1  VCELL16_HI/LO
          2. 9.5.4.6.2  VCELL15_HI/LO
          3. 9.5.4.6.3  VCELL14_HI/LO
          4. 9.5.4.6.4  VCELL13_HI/LO
          5. 9.5.4.6.5  VCELL12_HI/LO
          6. 9.5.4.6.6  VCELL11_HI/LO
          7. 9.5.4.6.7  VCELL10_HI/LO
          8. 9.5.4.6.8  VCELL9_HI/LO
          9. 9.5.4.6.9  VCELL8_HI/LO
          10. 9.5.4.6.10 VCELL7_HI/LO
          11. 9.5.4.6.11 VCELL6_HI/LO
          12. 9.5.4.6.12 VCELL5_HI/LO
          13. 9.5.4.6.13 VCELL4_HI/LO
          14. 9.5.4.6.14 VCELL3_HI/LO
          15. 9.5.4.6.15 VCELL2_HI/LO
          16. 9.5.4.6.16 VCELL1_HI/LO
          17. 9.5.4.6.17 BUSBAR_HI/LO
          18. 9.5.4.6.18 TSREF_HI/LO
          19. 9.5.4.6.19 GPIO1_HI/LO
          20. 9.5.4.6.20 GPIO2_HI/LO
          21. 9.5.4.6.21 GPIO3_HI/LO
          22. 9.5.4.6.22 GPIO4_HI/LO
          23. 9.5.4.6.23 GPIO5_HI/LO
          24. 9.5.4.6.24 GPIO6_HI/LO
          25. 9.5.4.6.25 GPIO7_HI/LO
          26. 9.5.4.6.26 GPIO8_HI/LO
          27. 9.5.4.6.27 DIETEMP1_HI/LO
          28. 9.5.4.6.28 DIETEMP2_HI/LO
          29. 9.5.4.6.29 AUX_CELL_HI/LO
          30. 9.5.4.6.30 AUX_GPIO_HI/LO
          31. 9.5.4.6.31 AUX_BAT_HI/LO
          32. 9.5.4.6.32 AUX_REFL_HI/LO
          33. 9.5.4.6.33 AUX_VBG2_HI/LO
          34. 9.5.4.6.34 AUX_AVAO_REF_HI/LO
          35. 9.5.4.6.35 AUX_AVDD_REF_HI/LO
          36. 9.5.4.6.36 AUX_OV_DAC_HI/LO
          37. 9.5.4.6.37 AUX_UV_DAC_HI/LO
          38. 9.5.4.6.38 AUX_OT_OTCB_DAC_HI/LO
          39. 9.5.4.6.39 AUX_UT_DAC_HI/LO
          40. 9.5.4.6.40 AUX_VCBDONE_DAC_HI/LO
          41. 9.5.4.6.41 AUX_VCM_HI/LO
          42. 9.5.4.6.42 REFOVDAC_HI/LO
          43. 9.5.4.6.43 DIAG_MAIN_HI/LO
          44. 9.5.4.6.44 DIAG_AUX_HI/LO
        7. 9.5.4.7  Balancing Configuration, Control and Status
          1. 9.5.4.7.1  CB_CELL16_CTRL through CB_CELL1_CTRL
          2. 9.5.4.7.2  VMB_DONE_THRESH
          3. 9.5.4.7.3  MB_TIMER_CTRL
          4. 9.5.4.7.4  VCB_DONE_THRESH
          5. 9.5.4.7.5  OTCB_THRESH
          6. 9.5.4.7.6  BAL_CTRL1
          7. 9.5.4.7.7  BAL_CTRL2
          8. 9.5.4.7.8  BAL_CTRL3
          9. 9.5.4.7.9  CB_COMPLETE1
          10. 9.5.4.7.10 CB_COMPLETE2
          11. 9.5.4.7.11 BAL_TIME
        8. 9.5.4.8  Protector Configuration and Control
          1. 9.5.4.8.1 OV_THRESH
          2. 9.5.4.8.2 UV_THRESH
          3. 9.5.4.8.3 UV_DISABLE1
          4. 9.5.4.8.4 UV_DISABLE2
          5. 9.5.4.8.5 OTUT_THRESH
          6. 9.5.4.8.6 OVUV_CTRL
          7. 9.5.4.8.7 OTUT_CTRL
        9. 9.5.4.9  GPIO Configuration
          1. 9.5.4.9.1 GPIO_CONF1
          2. 9.5.4.9.2 GPIO_CONF2
          3. 9.5.4.9.3 GPIO_CONF3
          4. 9.5.4.9.4 GPIO_CONF4
        10. 9.5.4.10 SPI Master
          1. 9.5.4.10.1 SPI_CONF
          2. 9.5.4.10.2 SPI_EXE
          3. 9.5.4.10.3 SPI_TX3, SPI_TX2, and SPI_TX1
          4. 9.5.4.10.4 SPI_RX3, SPI_RX2, and SPI_RX1
        11. 9.5.4.11 Diagnostic Control
          1. 9.5.4.11.1  DIAG_OTP_CTRL
          2. 9.5.4.11.2  DIAG_COMM_CTRL
          3. 9.5.4.11.3  DIAG_PWR_CTRL
          4. 9.5.4.11.4  DIAG_CBFET_CTRL1
          5. 9.5.4.11.5  DIAG_CBFET_CTRL2
          6. 9.5.4.11.6  DIAG_COMP_CTRL1
          7. 9.5.4.11.7  DIAG_COMP_CTRL2
          8. 9.5.4.11.8  DIAG_COMP_CTRL3
          9. 9.5.4.11.9  DIAG_COMP_CTRL4
          10. 9.5.4.11.10 DIAG_PROT_CTRL
        12. 9.5.4.12 Fault Configuration and Reset
          1. 9.5.4.12.1 FAULT_MSK1
          2. 9.5.4.12.2 FAULT_MSK2
          3. 9.5.4.12.3 FAULT_RST1
          4. 9.5.4.12.4 FAULT_RST2
        13. 9.5.4.13 Fault Status
          1. 9.5.4.13.1  FAULT_SUMMARY
          2. 9.5.4.13.2  FAULT_COMM1
          3. 9.5.4.13.3  FAULT_COMM2
          4. 9.5.4.13.4  FAULT_COMM3
          5. 9.5.4.13.5  FAULT_OTP
          6. 9.5.4.13.6  FAULT_SYS
          7. 9.5.4.13.7  FAULT_PROT1
          8. 9.5.4.13.8  FAULT_PROT2
          9. 9.5.4.13.9  FAULT_OV1
          10. 9.5.4.13.10 FAULT_OV2
          11. 9.5.4.13.11 FAULT_UV1
          12. 9.5.4.13.12 FAULT_UV2
          13. 9.5.4.13.13 FAULT_OT
          14. 9.5.4.13.14 FAULT_UT
          15. 9.5.4.13.15 FAULT_COMP_GPIO
          16. 9.5.4.13.16 FAULT_COMP_VCCB1
          17. 9.5.4.13.17 FAULT_COMP_VCCB2
          18. 9.5.4.13.18 FAULT_COMP_VCOW1
          19. 9.5.4.13.19 FAULT_COMP_VCOW2
          20. 9.5.4.13.20 FAULT_COMP_CBOW1
          21. 9.5.4.13.21 FAULT_COMP_CBOW2
          22. 9.5.4.13.22 FAULT_COMP_CBFET1
          23. 9.5.4.13.23 FAULT_COMP_CBFET2
          24. 9.5.4.13.24 FAULT_COMP_MISC
          25. 9.5.4.13.25 FAULT_PWR1
          26. 9.5.4.13.26 FAULT_PWR2
          27. 9.5.4.13.27 FAULT_PWR3
        14. 9.5.4.14 Debug Control and Status
          1. 9.5.4.14.1  DEBUG_CTRL_UNLOCK
          2. 9.5.4.14.2  DEBUG_COMM_CTRL1
          3. 9.5.4.14.3  DEBUG_COMM_CTRL2
          4. 9.5.4.14.4  DEBUG_COMM_STAT
          5. 9.5.4.14.5  DEBUG_UART_RC
          6. 9.5.4.14.6  DEBUG_UART_RR_TR
          7. 9.5.4.14.7  DEBUG_COMH_BIT
          8. 9.5.4.14.8  DEBUG_COMH_RC
          9. 9.5.4.14.9  DEBUG_COMH_RR_TR
          10. 9.5.4.14.10 DEBUG_COML_BIT
          11. 9.5.4.14.11 DEBUG_COML_RC
          12. 9.5.4.14.12 DEBUG_COML_RR_TR
          13. 9.5.4.14.13 DEBUG_UART_DISCARD
          14. 9.5.4.14.14 DEBUG_COMH_DISCARD
          15. 9.5.4.14.15 DEBUG_COML_DISCARD
          16. 9.5.4.14.16 DEBUG_UART_VALID_HI/LO
          17. 9.5.4.14.17 DEBUG_COMH_VALID_HI/LO
          18. 9.5.4.14.18 DEBUG_COML_VALID_HI/LO
          19. 9.5.4.14.19 DEBUG_OTP_SEC_BLK
          20. 9.5.4.14.20 DEBUG_OTP_DED_BLK
        15. 9.5.4.15 OTP Programming Control and Status
          1. 9.5.4.15.1 OTP_PROG_UNLOCK1A through OTP_PROG_UNLOCK1D
          2. 9.5.4.15.2 OTP_PROG_UNLOCK2A through OTP_PROG_UNLOCK2D
          3. 9.5.4.15.3 OTP_PROG_CTRL
          4. 9.5.4.15.4 OTP_ECC_TEST
          5. 9.5.4.15.5 OTP_ECC_DATAIN1 through OTP_ECC_DATAIN9
          6. 9.5.4.15.6 OTP_ECC_DATAOUT1 through OTP_ECC_DATAOUT9
          7. 9.5.4.15.7 OTP_PROG_STAT
          8. 9.5.4.15.8 OTP_CUST1_STAT
          9. 9.5.4.15.9 OTP_CUST2_STAT
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Base Device Application Circuit
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Cell Sensing and Balancing Inputs
          2. 10.2.1.2.2 BAT and External NPN
          3. 10.2.1.2.3 Power Supplies, Reference Input
          4. 10.2.1.2.4 GPIO For Thermistor Inputs
          5. 10.2.1.2.5 Internal Balancing Current
          6. 10.2.1.2.6 UART, NFAULT
          7. 10.2.1.2.7 Daisy Chain Isolation
            1. 10.2.1.2.7.1 Devices Connected on the Same PCB
            2. 10.2.1.2.7.2 Devices Connected on Different PCBs
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Daisy Device Application Circuit
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Ground Planes
      2. 12.1.2 Bypass Capacitors for Power Supplies and Reference
      3. 12.1.3 Cell Voltage Sensing
      4. 12.1.4 Daisy Chain Communication
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5 Electrical Characteristics

over operating -40℃ to 125℃ free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
THERMAL SHUTDOWN
TSHUT Thermal shutdown (rising direction) 130 137 152 °C
TSHUT_FALL Thermal shutdown (falling direction) 112 129 °C
TSHUT_HYS Thermal shutdown (rising - falling direction) 20 °C
TWARN_RANGE Thermal warning Threshold (rising direction) 85 115 °C
TWARN_HYS Thermal warning hysteresis (falling direction) 10 °C
TWARN_ACC Thermal warning accuracy (+/-) 5 °C
SUPPLY CURRENTS
ISHDN Supply current in SHUTDOWN mode Sum of both IBAT and ILDOIN 16 23 µA
ISLP(IDLE) Baseline supply current in SLEEP mode. No fault, no protector comparator, no cell balancing Sum of both IBAT and ILDOIN
TA = -20℃ to 65℃		 120 160 µA
Sum of both IBAT and ILDOIN
TA = -40℃ to 125℃		 220 µA
IACT(IDLE) Baseline supply current in ACTIVE mode Sum of both IBAT and ILDOIN
No fault, no communication, no protector comparator, no cell balancing		 10.4 11.6 mA
ICB_EN Additional supply current when cell balancing is on At least 1 cell balancing FET is on, OTCB is enabled. Other functions are inactive 1 1.5 mA
IPROTCOMP Additional supply current when protector comparator is on Either OV/UV/OT/UT protector is enabled. Other functions are inactive 20 60 µA
ITSREF SLEEP Mode, no load on TSREF pin 100 µA
IADC Additional supply current when ADC is enabled One ADC on, and conversion is in progress. Other functions are inactive 0.4 0.6 mA
2 ADCs on, and conversion is in progress. Other functions are inactive 0.6 0.9 mA
IBAT Supply current goes into BAT pin ACTIVE Mode 150 µA
SLEEP Mode 25 µA
SHUTDOWN Mode 5 µA
ICOMT Additional supply current during daisy-chain broadcast read of 128-byte data Use transformer isolation for daisy-chain interface 10 mA
ICOMC Additional supply current during daisy-chain broadcast read of 128-byte data Use capacitor or capacitor and choke isolation for daisy-chain interface 10 mA
IOW_SINK Sink current for open wire test, applies to VC1 to VC16 and CB1 to CB 16 380 500 600 µA
IOW_SOURCE Source current for open wire test, applies to VC0 and CB0 380 500 600 µA
ILEAK Leakage current on VC, CB pins VC, CB pins with ADC off.
 		 0.1 µA
Supplies (LDOIN)
VLDOIN LDOIN voltage No OTP programming 5.9 6 6.1 V
 OTP programming 7.9 8 8.1 V
Supplies (CVDD)
VCVDD CVDD output voltage ACTIVE and SLEEP mode 4.9 5 5.1 V
SHUTDOWN mode, no external Iload 3.95 6 V
SHUTDOWN mode, max external Iload = 5mA 3.4 5.5 V
VCVDD_LDRG CVDD load regulation ACTIVE/SLEEP mode, max external Iload = 10mA –30 30 mV
VCVDD_OV CVDD OV threshold ACTIVE/SLEEP mode, max external Iload = 10mA 5.3 5.5 5.7 V
VCVDD_OVHYS CVDD OV Hystersis ACTIVE/SLEEP mode, max external Iload = 10mA 130 150 170 mV
VCVDD_UV CVDD UV threshold SHUTDOWN mode 3.5 V
ACTIVE/SLEEP mode, max external Iload = 10mA 4.3 4.45 4.65 V
VCVDD_UVHYS CVDD UV Hystersis 260 mV
VCVDD_ILIMIT CVDD current limit ACTIVE, SLEEP 35 60 85 mA
Supplies (AVDD)
VAVDD AVDD output voltage CSUPPLIES = 1µF, ACTIVE mode 4.85 5 5.21 V
VAVDD_OV AVDD OV threshold CSUPPLIES = 1µF, ACTIVE mode 5.25 5.5 5.7 V
VAVDD_OVHYS AVDD OV Hystersis CSUPPLIES = 1µF, ACTIVE mode 135 155 165 mV
VAVDD_UV AVDD UV threshold CSUPPLIES = 1µF, ACTIVE mode 4.25 4.45 4.6 V
VAVDD_UVHYS AVDD UV Hystersis CSUPPLIES = 1µF, ACTIVE mode 235 340 430 mV
VAVDD_ILIMIT AVDD current limit CSUPPLIES = 1µF 10 30 50 mA
Supplies (DVDD)
VDVDD CSUPPLIES = 1µF, ACTIVE mode 1.72 1.8 1.88 V
VDVDD_OV DVDD OV threshold  CSUPPLIES = 1µF, ACTIVE mode 1.95 2.1 2.3 V
VDVDD_OVHYS DVDD OV Hystersis CSUPPLIES = 1µF, ACTIVE mode 40 65 120 mV
VDVDD_UV DVDD UV threshold  CSUPPLIES = 1µF, ACTIVE mode 1.623 1.65 1.71 V
VDVDD_UVHYS DVDD UV Hystersis CSUPPLIES = 1µF, ACTIVE mode 15 50 73 mV
VDVDD_ILIMIT DVDD current limit 13 30 53 mA
Supplies (TSREF)
VTSREF TSREF output voltage CSUPPLIES = 1µF, ACTIVE mode 4.975 5 5.025 V
VTSREF_LDRG TSREF load regulation Iload = 4mA, CSUPPLIES = 1µF, ACTIVE mode –30 30 mV
VTSREF_OV TSREF OV threshold Iload = 4mA, CSUPPLIES = 1µF, ACTIVE mode 5.2 5.6 5.8 V
VTSREF_OVHYS TSREF OV Hystersis Iload = 4mA, CSUPPLIES = 1µF, ACTIVE mode 98 110 120 mV
VTSREF_UV TSREF UV threshold Iload = 4mA, CSUPPLIES = 1µF, ACTIVE mode 4.0 4.2 4.4 V
VTSREF_UVHYS TSREF UV Hystersis Iload = 4mA, CSUPPLIES = 1µF, ACTIVE mode 300 350 400 mV
VTSREF_ILIMIT TSREF current limit Device in ACTIVE Mode 15 30 52 mA
Negative Charge Pump (NEG5V)
VNEG5V CNEG5V = 0.1µF -5.0 -4.6 -4.5 V
VNEG5V_UV NEG5V UV threshold (rising) CNEG5V = 0.1µF -4.1 -3.5 -3.0 V
VNEG5V_UVRECOV NEG5V UV Recovery CNEG5V = 0.1µF -4.3 -3.8 -3.3 V
CELL BALANCE
RDSON Internal cell balance FET Rdson VCn > 2.8V, where n = 1 to 16; -40oC<TA<125oC 1.45 4.6 Ω
VCB_DONE VCB_DONE detection threhsold setting range (not accuracy) Step of 25mV 2.45 4 V
VMB_DONE VMB_DONE detection threhsold setting range (not accuracy) Step of 1V 18 65 V
TOTCB OTCB threshold setting range (not accuracy) Step of 2% 10 24 %
TCOOLOFF COOLOFF threshold setting range (not accuracy) Step of 2% 4 14 %
TCB_WARN CB TWARN threshold 105 oC
TCB_WARN_HYS CB TWARN Hysteresis 10 oC
ADC Resolution
ENOBMAIN Main ADC Effective number of
bits		     16   bits
ENOBAUX AUX ADC Effective number of bits     14   bits
VLSB_ADC Main and AUX ADC Resolution for VCELL measurement   190.73   µV/LSB
VLSB_BB Main and AUX ADC Resolution for (BBP-BBN) measurement 30.52 µV/LSB
VLSB_MAIN_DIETEMP1 DieTemp1 resolution (Main ADC) ADC measurement is centered with 0x000 = 0oC   0.025   °C/LSB
VLSB_AUX_DIETEMP2 DieTemp2 resolution (AUX ADC) ADC measurement is centered with 0x000 = 0oC   0.025   °C/LSB
VLSB_AUX_BAT BAT resolution (AUX ADC) Applies to BAT voltage measurement from AUX ADC   3.05   mV/LSB
VLSB_GPIO GPIO resolution (Main & AUX
ADC)		   152.59   µV/LSB
VLSB_TSREF TSREF resolution (Main ADC) 169.54 µV/LSB
VLSB_DIAG Diagnostic measurements resolution
 		 REFL, VBG2, LPBG5, VCM, AVAO_REF, AVDD_REF, HW protector DAC
 		   152.59   µV/LSB
VLSB_DIAG
 		 OV_DAC, UV_DAC, VCBDONE_DAC
 		   190.73   µV/LSB
ADC Accuracy
IVC_DELTA VCn to VCn-1 input current delta (when Main ADC is on) TA = -20oC to 65oC     1.8 µA
TA = -40oC to 105oC     2 µA
IVC VCn input current (when Main ADC is on)     8 12 µA
RCB_INPUT CB pin input impedance (when AUX ADC is on) 16 MΩ
VACC_MAIN_CELL Total channel accuracy for main ADC VCELL measurement, LPF_VCELL[2:0] = 0x03 setting; 2V<VCELL<4.5V; TA=25oC -2.2 1.5 mV
2V<VCELL<4.5V; -20oC<TA<65oC -3.0 2.4 mV
2V<VCELL<4.5V; -40oC<TA<105oC -3.5 2.6 mV
2V<VCELL<4.5V; -40oC<TA<125oC -3.5 2.6 mV
1V<VCELL< 5V; -40oC<TA<125oC -3.7 2.8 mV
-2V<VCELL< 5V; -40oC<TA<125oC -4.5 3.2 mV
VACC_AUX_CELL Total channel accuracy for AUX ADC measurement (excluding BAT and GPIO accuracy); 2V<VCELL<4.5V; TA=25oC -7.5 5.4 mV
2V<VCELL<4.5V; -20oC<TA<65oC -8.0 6.3 mV
2V<VCELL<4.5V; -40oC<TA<105oC -9.0 6.3 mV
2V<VCELL<4.5V; -40oC<TA<125oC -9.0 6.5 mV
1V<VCELL< 5V; -40oC<TA<125oC -9.0 6.6 mV
0V<VCELL< 5V; -40oC<TA<125oC -9.0 6.6 mV
V(MAIN-AUX) Main - AUX measurement during VCELL and OVDAC Reference diagnostic. Same input voltage to both ADC under same TA; 2V<VCELL<4.5V; TA=25oC -7.1   6.1 mV
2V<VCELL<4.5V; -20oC<TA<65oC -7.8   6.6 mV
2V<VCELL<4.5V; -40oC<TA<105oC -7.8   6.6 mV
2V<VCELL<4.5V; -40oC<TA<125oC -7.8 6.7 mV
1V<VCELL< 5V; -40oC<TA<125oC -7.9 6.9 mV
0V<VCELL< 5V; -40oC<TA<125oC -7.9   6.9 mV
VACC_MAIN_GPIO_RATIO Measured GPIO from Main ADC/measured TSREF from Main ADC; 0.08V<VIN<0.2V, 85oC<TA<125oC -0.20 0.20 %
0.2V<VIN<4.6V, -40oC<TA<105oC -0.20 0.20 %
4.6V<VIN<4.8V, -40oC<TA<-20oC -0.30 0.30 %
VACC_AUX_GPIO_RATIO Measured GPIO from AUX ADC/measured TSREF from AUX ADC; 0.08V<VIN<0.2V, 85oC<TA<125oC -0.20 0.20 %
0.2V<VIN<4.6V, -40oC<TA<105oC -0.20 0.20 %
4.6V<VIN<4.8V, -40oC<TA<-20oC -0.30 0.30 %
VACC_MAIN_GPIO_ABS Total channel accuracy for GPIO measurement (Main ADC); 0.08V<VIN<0.2V, 85oC<TA<125oC -4.00 4.00 mV
0.2V<VIN<4.6V, -40oC<TA<105oC -5.00 3.00 mV
4.6V<VIN<4.8V, -40oC<TA<-20oC -4.00 4.00 mV
VACC_AUX_GPIO_ABS Accuracy from AUX ADC on GPIO 0.08V<VIN<0.2V, 85oC<TA<125oC -6.00 6.00 mV
0.2V<VIN<4.6V, -40oC<TA<105oC -6.00 6.00 mV
4.6V<VIN<4.8V, -40oC<TA<-20oC -6.00 6.00 mV
VACC_MAIN_BB Total channel accuracy for (BBP-BBN) from Main ADC LPF_BB[2:0] = 0x00 -1.1 1.1 mV
VACC_AUX_BB Total channel accuracy for (BBP-BBN) from AUXADC -4 4 mV
VACC_AUX_BAT AUX ADC measurement accuracy for BAT pin Vbat pack range: 32V to 72V, TA = -40oC to 125oC -225   135 mV
VACC_AUX_REFL AUX ADC measurement result 1.092 1.1 1.106 V
VACC_AUX_VBG2 AUX ADC measurement result 1.092 1.1 1.106 V
VACC_AUX_VCM AUX ADC measurement result 2.400 2.5 2.550 V
VACC_AUX_AVAO_REF AUX ADC measurement result 2.400 2.47 2.550 V
VACC_AUX_AVDD_REF AUX ADC measurement result 2.400 2.47 2.550 V
VACC_AUX_OVDAC AUX ADC measurement result Setting at 4.475V; TA = -20oC to 65oC 4.450 4.500 V
VACC_AUX_OVDAC AUX ADC measurement result Setting at 4.475V; TA = -40oC to 105oC 4.445 4.500 V
VACC_AUX_OVDAC AUX ADC measurement result Setting at 4.475V; TA = -40oC to 125oC 4.445 4.500 V
VACC_AUX_OVDAC AUX ADC measurement result Setting at 3.8V 3.770 3.825 V
VACC_AUX_OVDAC AUX ADC measurement result Setting at 3V 2.970 3.030 V
VACC_AUX_UVDAC AUX ADC measurement result Setting at 3.1V 3.095 3.1 3.150 V
VACC_AUX_VCBDONEDAC AUX ADC measurement result Setting at 4V 3.950 4 4.050 V
VACC_AUX_OTDAC AUX ADC measurement result Setting at 39% 1.900 1.95 2.000 V
VACC_AUX_UTDAC AUX ADC measurement result Setting at 80% 3.950 4 4.050 V
VACC_MAIN_TSREF Main ADC measurement result 4.975 5 5.025 V
VACC_MAIN__DIETEMP Total channel accuracy for Die Temp1 measurement (+/-) 3 ℃
VACC_AUX_DIETEMP Total channel accuracy for Die Temp2 measurement (+/-) 6 ℃
Reference Voltages
VREFH REFHP to REFHM voltage 4.975 5 5.025 V
HW Voltage Comparator/Protector (CELL OV/UV)
VOV_COMP_RANGE OV comparator detection threshold setting range (not accuracy) Step of 25mV 2700   3000 mV
Step of 25mV 3600   3800 mV
Step of 25mV 4175   4500 mV
VOV_COMP_HYS OV comparator hysteresis after
detection		     50   mV
VOV_COMP_ACC OV comparator accuracy TA = -20oC to 65oC -24   24 mV
TA = -40oC to 105oC -28   28 mV
VUV_COMP_RANGE UV comparator detection threshold  setting range (not accuracy) Step of 50mV 1200   3100 mV
VUV_COMP_HYS UV comparator hysteresis after detection     50   mV
VUV_COMP_ACC UV comparator accuracy TA = -20oC to 65oC -35   35 mV
TA = -40oC to 105oC -50   50 mV
HW Temperature Comparator/Protector (NTC OT/UT)
VOT_COMP_RANGE OT comparator detection threshold setting range (not accuracy) Step of 1%, ratiometric with respect to TSREF 10   39 %
VOT_COMP_HYS OT comparator hysteresis after detection     2   %
VOT_COMP_ACC OT comparator accuracy   -0.5   0.5 %
VUT_COMP_RANGE UT comparator detection threshold  range Step of 2%, ratiometric with respect to TSREF 66   80 %
VUT_COMP_HYS UT comparator hysteresis after detection     2   %
VUT_COMP_ACC UT comparator accuracy   -0.5   0.5 %
Digital I/Os (TX, RX, GPIO, SPI master)
VOH Output as logic level high (TX, GPIO as output) GPIO is configured as output. IOUT = 1mA VCVDD-0.3     V
VOL Output as logic level low (TX, NFAULT, GPIO as output) GPIO is configured as output. IOUT = 1mA     0.3 V
VIH Input as logic level high (RX, GPIO as fault input) GPIO is configured as input. IOUT = 1mA 0.75 x VCVDD     V
VIL Input as logic level low (RX, GPIO as fault input) GPIO is configured as input. IOUT = 1mA     0.25 x VCVDD V
RWK_PU GPIO weak pull-up resistance 20 37 60 KΩ
RWK_PD GPIO weak pull-down resistance 20 40 60 KΩ
COML and COMH
RDCTX Transmitter output impedance (COML and COMH) 18 Ω
RDCCM Common mode impedance (COML and COMH)   45   kΩ
VDCCM Common mode voltage  (COML and COMH) 2.21 2.5 2.76 V
VCOMM_DATA1 Receiver threshold range (VCOMP-VCOML) form communication CODE:0 0.4 1.2 V
VCOMM_TONE1 Receiver threshold range (VCOMP-VCOML) form Tone CODE:0 0.4 1.2 V