SBOS571C August   2011  – August 2018 BUF20800-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 General-call Reset and Power-up
      2. 7.3.2 Output Voltage
      3. 7.3.3 Output Latch
      4. 7.3.4 Programmable VCOM
      5. 7.3.5 REFH and REFL Input range
    4. 7.4 Device Functional Modes
      1. 7.4.1 Replacement of Traditional Gamma Buffer
      2. 7.4.2 Dynamic Gamma Control
    5. 7.5 Programming
      1. 7.5.1 Two-wire Bus Overview
      2. 7.5.2 Data Rates
      3. 7.5.3 Read/Write Operations
        1. 7.5.3.1 Writing
        2. 7.5.3.2 Reading
      4. 7.5.4 Register Maps
        1. 7.5.4.1 Addressing the BUF20800-Q1
      5. 7.5.5 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor Selection
        2. 8.2.2.2 REFH and REFL Voltage Settings
      3. 8.2.3 Application Curves
      4. 8.2.4 Configuration for 20 Gamma Channels
      5. 8.2.5 Configuration for 22 Gamma Channels
      6. 8.2.6 The BUF20800-Q1 in Industrial Applications
      7. 8.2.7 Total TI Panel Solution
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General PowerPAD Design Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

At TA = 25°C, VS = 18 V, VSD = 5 V, RL = 1.5 kΩ connected to ground, and CL = 200 pF, unless otherwise noted.
PARAMETER CONDITIONS BUF20800-Q1 UNIT
MIN TYP MAX
ANALOG GAMMA BUFFER CHANNELS
OUT 1−9 output swing: high Sourcing 10 mA, VREFH = 17.8 V, Code 1023,
TA = –40°C to +105°C		 17.6 V
Sourcing 10 mA, VREFH = 17.8 V, Code 1023,
TA = +25°C 		17.7 17.8
OUT 10−18 output swing: high Sourcing 10 mA, VREFH = 17.8 V, Code 978,
TA = –40°C to +105°C		 16.8 17.2
OUT 1−9 output swing: low Sinking 10 mA, VREFL = 0.2 V, Code 32,
TA = –40°C to +105°C		 0.6 1.0 V
OUT 10−18 output swing: low Sinking 10 mA, VREFL = 0.2 V, Code 00,
TA = –40°C to +105°C		 0.2 0.4
VCOM buffer output swing: high Sourcing 50 mA, VREFH =17.8 V,
TA = –40°C to +105°C		 13 15.5 V
VCOM buffer output swing: low Sinking 50 mA, VREFL = 0.2 V,
TA = –40°C to +105°C		 1 2.0 V
IO Output current (1) All Channels, Code 512, Sinking/Sourcing 40 45 mA
INL Integral nonlinearity No Load, VREFH = 17 V, VREFL = 1 V 0.3 1.5 Bits
No Load, VREFH = 17 V, VREFL = 1 V, TA = –40°C to 105°C 2.5
DNL Differential nonlinearity No Load, VREFH = 17 V, VREFL = 1 V 0.3 1 Bits
Gain error 0.12 %
tD Program to out delay 5 μs
Output accuracy No Load, VREFH = 17 V, VREFL = 1 V ±20 ±50 mV
No Load, VREFH = 17 V, VREFL = 1 V,
TA = –40°C to +105°C		 ±25 mV
RINH Input resistance at VREFH and VREFL 100 MΩ
REG Load regulation, All References VOUT = VS/2,
IOUT = 5 mA to –5 mA Step		 0.5 1.5 mV/mA
40 mA, All Channels VOUT = VS/2,
ISINKING = 40 mA, ISOURCING = 40 mA		 0.5 1.5 mV/mA
ANALOG POWER SUPPLY
VS Operating range 7 18 V
IS Total analog supply current No Load 18 28 mA
Outputs at Reset Values, No Load, Two-Wire Bus Inactive,
TA = –40°C to +105°C		 28 mA
DIGITAL
VIH Logic 1 input voltage 0.7 × VSD V
VIL Logic 0 input voltage 0.3 × VSD V
VOL Logic 0 output voltage ISINK = 3 mA 0.15 0.4 V
Input leakage ±0.01 ±10 μA
fCLK Clock frequency Standard/Fast Mode, TA = –40°C to +105°C 400 kHz
High-Speed Mode, TA = –40°C to +105°C 3.4 MHz
DIGITAL POWER SUPPLY
VSD Operating range 2.0 5.5 V
ISD Digital supply current (2) Outputs at Reset Values, No Load, Two-Wire Bus Inactive 25 50 μA
Outputs at Reset Values, No Load, Two-Wire Bus Inactive,
TA = –40°C to +105°C		 100 μA
TEMPERATURE RANGE
Operating temperature range Junction Temperature < +125°C –40 +105 °C
Storage temperature range –65 +150 °C
θJA Thermal resistance, HTSSOP-38:
Junction-to-Ambient		 30 °C/W
θJC Thermal resistance, HTSSOP-38:
Junction-to-Case		 15 °C/W
1. See typical characteristic graph Output Voltage vs Output Current
2. See typical characteristic graph Digital Supply Current vs Temperature