SCAS918E June   2013  – August 2024 CDCE913-Q1 , CDCEL913-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Control Terminal Configuration
      2. 8.3.2 Default Device Configuration
      3. 8.3.3 I2C Serial Interface
      4. 8.3.4 Data Protocol
    4. 8.4 Device Functional Modes
      1. 8.4.1 SDA and SCL Hardware Interface
    5. 8.5 Programming
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Spread-Spectrum Clock (SSC)
        2. 9.2.2.2 PLL Frequency Planning
        3. 9.2.2.3 Crystal Oscillator Start-Up
        4. 9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 9.2.2.5 Unused Inputs and Outputs
        6. 9.2.2.6 Switching Between XO and VCXO Mode
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Register Maps
    1. 10.1 I2C Configuration Registers
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 I2C Configuration Registers

The clock input, control pins, PLLs, and output stages are user-configurable. The following tables and explanations describe the programmable functions of the CDCE913-Q1 and CDCEL913-Q1 devices. All settings can be manually written into the device through the I2C bus, or programmed by using the TI Pro-Clock™ software. TI Pro-Clock™ software allows the user to make all settings quickly, and automatically calculates the values for optimized performance at lowest jitter.

Table 10-1 I2C Registers
ADDRESS OFFSETREGISTER DESCRIPTIONTABLE
00hGeneric configuration registerTable 10-3
10hPLL1 configuration registerTable 10-4

The grey-highlighted bits, described in the configuration register tables in the following pages, belong to the control terminal register. The user can predefine up to eight different control settings. These settings then can be selected by the external control pins, S0, S1, and S2. See the Control Terminal Configuration section.

Table 10-2 Configuration Register, External Control Terminals
Y1PLL1 Settings
EXTERNAL CONTROL PINSOUTPUT SELECTIONFREQUENCY SELECTIONSSC SELECTIONOUTPUT SELECTION
S2S1S0Y1FS1SSC1Y2Y3
0000Y1_0FS1_0SSC1_0Y2Y3_0
1001Y1_1FS1_1SSC1_1Y2Y3_1
2010Y1_2FS1_2SSC1_2Y2Y3_2
3011Y1_3FS1_3SSC1_3Y2Y3_3
4100Y1_4FS1_4SSC1_4Y2Y3_4
5101Y1_5FS1_5SSC1_5Y2Y3_5
6110Y1_6FS1_6SSC1_6Y2Y3_6
7111Y1_7FS1_7SSC1_7Y2Y3_7
Address offset(1)04h13h10h–12h15h
(1) Address offset refers to the byte address in the configuration register in Table 10-3 and Table 10-4.
Table 10-3 Generic Configuration Register
OFFSET(1) BIT(2) ACRONYM DEFAULT(3) DESCRIPTION
00h 7 E_EL Xb Device identification (read-only): 1 is CDCE913-Q1 (3.3 V out), 0 is CDCEL913-Q1 (1.8 V out)
6:4 RID Xb Revision identification number (read-only)
3:0 VID 1h Vendor identification number (read-only)
01h 7 — 0b Reserved – always write 0
6 EEPIP 0b EEPROM programming Status:(4) (read-only) 0 – EEPROM programming is completed.
1 – EEPROM is in programming mode.
5 EELOCK 0b Permanently lock EEPROM data(5) 0 – EEPROM is not locked.
1 – EEPROM is permanently locked.
4 PWDN 0b Device power down (overwrites S0, S1, and S2 settings; configuration register settings are unchanged)
Note: PWDN cannot be set to 1 in the EEPROM.
0 – Device active (PLL1 and all outputs are enabled)
1 – Device power down (PLL1 in power down and all outputs in Hi-Z state)
3:2 INCLK 00b Input clock selection: 00 – Xtal     10 – LVCMOS
01 – VCXO 11 – Reserved
1:0 TARGET_ADR 01b Address bits A0 and A1 of the target receiver address
02h 7 M1 1b Clock source selection for output Y1: 0 – Input clock  1 – PLL1 clock
6 SPICON 0b Operation mode selection for pins 12 and 13(6)
0 – Serial programming interface SDA (pin 13) and SCL (pin 12)
1 – Control pins S1 (pin 13) and S2 (pin 12)
5:4 Y1_ST1 11b Y1-State0/1 definition
3:2 Y1_ST0 01b 00 – Device power down (all PLLs in power down and all outputs in Hi-Z state)
01 – Y1 disabled to Hi-Z state		 10 – Y1 disabled to low
11 – Y1 enabled
1:0 Pdiv1 [9:8] 001h 10-bit Y1-output-divider Pdiv1: 0 – Divider reset and stand-by
1 to 1023 – Divider value
03h 7:0 Pdiv1 [7:0]
04h 7 Y1_7 0b Y1_x State selection(7) 0 – State0 (predefined by Y1_ST0)
1 – State1 (predefined by Y1_ST1)
6 Y1_6 0b
5 Y1_5 0b
4 Y1_4 0b
3 Y1_3 0b
2 Y1_2 0b
1 Y1_1 1b
0 Y1_0 0b
05h 7:3 XCSEL 0Ah Crystal load capacitor selection(8)
00h – 0 pF
01h – 1 pF
02h – 2 pF
:14h to 1Fh – 20 pF
2:0 0b Reserved – do not write other than 0
06h 7:1 BCOUNT 20h 7-bit byte count (defines the number of bytes which will be sent from this device at the next Block Read transfer); all bytes must be read out to finish the read cycle correctly.
0 EEWRITE 0b Initiate EEPROM write cycle (4)(9) 0– No EEPROM write cycle
1 – Start EEPROM write cycle (internal registers are saved to the EEPROM)
07h-0Fh — 0h Unused address range
(1) Writing data beyond 20h may affect device function.
(2) All data is transferred with the MSB first.
(3) Unless customer-specific setting
(4) During EEPROM programming, no data is allowed to be sent to the device through the I2C bus until the programming sequence is completed. However, data can be read out during the programming sequence (Byte Read or Block Read).
(5) If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. No further programming is possible. However, data can still be written through the I2C bus to the internal register to change device function quickly, but new data can no longer be saved to the EEPROM. EELOCK is effective only if written into the EEPROM.
(6) Selection of control pins is effective only if written into the EEPROM. When written into the EEPROM, the serial programming pins are no longer available. However, if VDDOUT is forced to GND, the two control pins, S1 and S2, temporarily act as serial programming pins (SDA-SCL), and the two target receiver address bits are reset to A0 = 0 and A1 = 0.
(7) These are the bits of the control terminal register (see Table 10-2 ). The user can predefine up to eight different control settings. These settings then can be selected by the external control pins, S0, S1, and S2.
(8) The internal load capacitor (C1, C2) must be used to achieve the best clock performance. External capacitors should be used only to finely adjust CL by a few picofarads. The value of CL can be programmed with a resolution of 1 pF for a crystal load range of 0 pF to
20 pF. For CL > 20 pF, use additional external capacitors. The device input capacitance value must be considered, which always adds 1.5 pF (6 pF//2 pF) to the selected CL. For more about VCXO config. and crystal recommendation, see VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).
(9) The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level-high does not trigger an EEPROM WRITE cycle. The EEWRITE bit must be reset to low after the programming is completed. The programming status can be monitored by reading out EEPIP. If EELOCK is set to high, no EEPROM programming is possible.
Table 10-4 PLL1 Configuration Register
OFFSET(1)BIT(2)ACRONYMDEFAULT(3)DESCRIPTION
10h7:5SSC1_7 [2:0]000bSSC1: PLL1 SSC selection (modulation amount). (4)
4:2SSC1_6 [2:0]000bDown
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%		Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
1:0SSC1_5 [2:1]000b
11h7SSC1_5 [0]
6:4SSC1_4 [2:0]000b
3:1SSC1_3 [2:0]000b
0SSC1_2 [2]000b
12h7:6SSC1_2 [1:0]
5:3SSC1_1 [2:0]000b
2:0SSC1_0 [2:0]000b
13h7FS1_70bFS1_x: PLL1 frequency selection(4)
6FS1_60b0 – fVCO1_0 (predefined by PLL1_0 – multiplier/divider value)
1 – fVCO1_1 (predefined by PLL1_1 – multiplier/divider value)
5FS1_50b
4FS1_40b
3FS1_30b
2FS1_20b
1FS1_10b
0FS1_00b
14h7MUX11bPLL1 multiplexer:0 – PLL1
1 – PLL1 bypass (PLL1 is in power down)
6M21bOutput Y2 multiplexer:0 – Pdiv1
1 – Pdiv2
5:4M310bOutput Y3 Multiplexer:00 – Pdiv1-divider
01 – Pdiv2-divider
10 – Pdiv3-divider
11 – Reserved
3:2Y2Y3_ST111bY2, Y3-State0/1definition:00 – Y2 and Y3 disabled to Hi-Z state (PLL1 is in power down)
01 – Y2 and Y3 disabled to Hi-Z state
10–Y2 and Y3 disabled to low
11 – Y2 and Y3 enabled
1:0Y2Y3_ST001b
15h7Y2Y3_70bY2Y3_x output state selection. (4)
6Y2Y3_60b0 – State0 (predefined by Y2Y3_ST0)
1 – State1 (predefined by Y2Y3_ST1)
5Y2Y3_50b
4Y2Y3_40b
3Y2Y3_30b
2Y2Y3_20b
1Y2Y3_11b
0Y2Y3_00b
16h7SSC1DC0bPLL1 SSC down or center selection:0 – Down
1 – Center
6:0Pdiv201h7-bit Y2-output-divider Pdiv2:0 – Reset and standby
1 to 127 – Divider value
17h7—0bReserved – do not write other than 0
6:0Pdiv301h7-bit Y3-output-divider Pdiv3:0 – Reset and standby
1 to 127 – Divider value
18h7:0PLL1_0N [11:4]004hPLL1_0(5): 30-bit multiplier or divider value for frequency fVCO1_0
(for more information, see PLL Frequency Planning).
19h7:4PLL1_0N [3:0]
3:0PLL1_0R [8:5]000h
1Ah7:3PLL1_0R[4:0]
2:0PLL1_0Q [5:3]10h
1Bh7:5PLL1_0Q [2:0]
4:2PLL1_0P [2:0]010b
1:0VCO1_0_RANGE00bfVCO1_0 range selection:00 – fVCO1_0 < 125 MHz
01 – 125 MHz ≤ fVCO1_0 < 150 MHz
10 – 150 MHz ≤ fVCO1_0 < 175 MHz
11 – fVCO1_0 ≥ 175 MHz
1Ch7:0PLL1_1N [11:4]004hPLL1_1(5): 30-bit multiplier or divider value for frequency fVCO1_1
(for more information, see PLL Frequency Planning).
1Dh7:4PLL1_1N [3:0]
3:0PLL1_1R [8:5]000h
1Eh7:3PLL1_1R[4:0]
2:0PLL1_1Q [5:3]10h
1Fh7:5PLL1_1Q [2:0]
4:2PLL1_1P [2:0]010b
1:0VCO1_1_RANGE00bfVCO1_1 range selection:00 – fVCO1_1 < 125 MHz
01 – 125 MHz ≤ fVCO1_1 < 150 MHz
10 – 150 MHz ≤ fVCO1_1 < 175 MHz
11 – fVCO1_1 ≥ 175 MHz
(1) Writing data beyond 20h may adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used
(4) The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external control pins, S0, S1, and S2.
(5) PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096