SCAS847I July   2007  – October 2016 CDCE925 , CDCEL925

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 EEPROM Specification
    7. 7.7 Timing Requirements: CLK_IN
    8. 7.8 Timing Requirements: SDA/SCL
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Control Terminal Setting
      2. 9.3.2 Default Device Setting
      3. 9.3.3 SDA/SCL Serial Interface
      4. 9.3.4 Data Protocol
    4. 9.4 Device Functional Modes
      1. 9.4.1 SDA/SCL Hardware Interface
    5. 9.5 Programming
    6. 9.6 Register Maps
      1. 9.6.1 SDA/SCL Configuration Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Spread Spectrum Clock (SSC)
        2. 10.2.2.2 PLL Multiplier/Divider Definition
        3. 10.2.2.3 Crystal Oscillator Start-Up
        4. 10.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 10.2.2.5 Unused Inputs and Outputs
        6. 10.2.2.6 Switching Between XO and VCXO Mode
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Related Links
    4. 13.4 Receiving Notification of Documentation Updates
    5. 13.5 Community Resources
    6. 13.6 Trademarks
    7. 13.7 Electrostatic Discharge Caution
    8. 13.8 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VDD –0.5 2.5 V
Input voltage, VI(2)(3) –0.5 VDD + 0.5 V
Output voltage, VO(2) –0.5 VDD + 0.5 V
Input current, II (VI < 0, VI > VDD) 20 mA
Continuous output current, IO 50 mA
Maximum junction temperature, TJ 125 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) SDA and SCL can go up to 3.6 V as stated in the Recommended Operating Conditions table.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VDD Device supply voltage 1.7 1.8 1.9 V
VDDOUT Output Yx supply voltage CDCE925 2.3 3.6 V
CDCEL925 1.7 1.9
VIL Low-level input voltage LVCMOS 0.3 × VDD V
VIH High-level input voltage LVCMOS 0.7 × VDD V
VI(thresh) Input voltage threshold LVCMOS 0.5 × VDD V
VI(S) Input voltage S0 0 1.9 V
S1, S2, SDA, SCL; V(Ithresh) = 0.5 VDD 0 3.6
VI(CLK) Input voltage, CLK 0 1.9 V
IOH /IOL Output current VDDOUT = 3.3 V ±12 mA
VDDOUT = 2.5 V ±10
VDDOUT = 1.8 V ±8
CL Output load LVCMOS 15 pF
TA Operating free-air temperature –40 85 °C
CRYSTAL AND VCXO(1)
fXtal Crystal input frequency (fundamental mode) 8 27 32 MHz
ESR Effective series resistance 100 Ω
fPR Pulling (0 V ≤ VCtrl ≤ 1.8 V)(2) ±120 ±150 ppm
VCtrl Frequency control voltage 0 VDD V
C0/C1 Pullability ratio 220
CL On-chip load capacitance at Xin and Xout 0 20 pF
(1) For more information about VCXO configuration, and crystal recommendation, see VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).
(2) Pulling range depends on crystal-type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of minimum ±120 ppm applies for crystal listed in VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).

7.4 Thermal Information

THERMAL METRIC(1) CDCEx925 UNIT
PW (TSSOP)
20 PINS
RθJA Junction-to-ambient thermal resistance Airflow 0 (LFM) 101 °C/W
Airflow 150 (LFM) 85
Airflow 200 (LFM) 84
Airflow 250 (LFM) 82
Airflow 500 (LFM) 74
RθJC(top) Junction-to-case (top) thermal resistance 42 °C/W
RθJB Junction-to-board thermal resistance 63.63 °C/W
ψJT Junction-to-top characterization parameter 1.01 °C/W
ψJB Junction-to-board characterization parameter 58.12 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 58 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
IDD Supply current (see Figure 1) All outputs off, fCLK = 27 MHz,
fVCO = 135 MHz, fOUT = 27 MHz		 All PLLS on 20 mA
Per PLL 9
IDDOUT Supply current (see Figure 2 and Figure 3) No load, all outputs on,
fOUT = 27 MHz		 CDCE925,
VDDOUT = 3.3 V		 2 mA
CDCEL925,
VDDOUT = 1.8 V		 1
IDDPD Power-down current. Every circuit powered down except SDA/SCL fIN = 0 MHz, VDD = 1.9 V 30 µA
VPUC Supply voltage VDD threshold for power-up control circuit 0.85 1.45 V
fVCO VCO frequency range of PLL 80 230 MHz
fOUT LVCMOS output frequency CDCEx925 VDDOUT = 1.8 V 230 MHz
LVCMOS
VIK LVCMOS input voltage VDD = 1.7 V, IS = –18 mA –1.2 V
II LVCMOS input current VI = 0 V or VDD, VDD = 1.9 V ±5 µA
IIH LVCMOS input current for S0/S1/S2 VI = VDD, VDD = 1.9 V 5 µA
IIL LVCMOS Input current for S0/S1/S2 VI = 0 V, VDD = 1.9 V –4 µA
CI Input capacitance at Xin/Clk VIClk = 0 V or VDD 6 pF
Input capacitance at Xout VIXout = 0 V or VDD 2
Input capacitance at S0/S1/S2 VIS = 0 V or VDD 3
CDCE925 – LVCMOS FOR VDDOUT = 3.3 V
VOH LVCMOS high-level output voltage VDDOUT = 3 V, IOH = –0.1 mA 2.9 V
VDDOUT = 3 V, IOH = –8 mA 2.4
VDDOUT = 3 V, IOH = –12 mA 2.2
VOL LVCMOS low-level output voltage VDDOUT = 3 V, IOL = 0.1 mA 0.1 V
VDDOUT = 3 V, IOL = 8 mA 0.5
VDDOUT = 3 V, IOL = 12 mA 0.8
tPLH, tPHL Propagation delay All PLL bypass 3.2 ns
tr/tf Rise and fall time VDDOUT = 3.3 V (20%–80%) 0.6 ns
tjit(cc) Cycle-to-cycle jitter(2)(3) 1 PLL switching, Y2-to-Y3 50 70 ps
2 PLL switching, Y2-to-Y5 90 130
tjit(per) Peak-to-peak period jitter(3) 1 PLL switching, Y2-to-Y3 60 100 ps
2 PLL switching, Y2-to-Y5 100 160
tsk(o) Output skew (4) fOUT = 50 MHz, Y1-to-Y3 70 ps
fOUT = 50 MHz, Y2-to-Y5 150
odc Output duty cycle (5) fVCO = 100 MHz, Pdiv = 1 45% 55%
CDCE925 – LVCMOS FOR VDDOUT = 2.5 V
VOH LVCMOS high-level output voltage VDDOUT = 2.3 V, IOH = –0.1 mA 2.2 V
VDDOUT = 2.3 V, IOH = –6 mA 1.7
VDDOUT = 2.3 V, IOH = –10 mA 1.6
VOL LVCMOS low-level output voltage VDDOUT = 2.3 V, IOL = 0.1 mA 0.1 V
VDDOUT = 2.3 V, IOL = 6 mA 0.5
VDDOUT = 2.3 V, IOL = 10 mA 0.7
tPLH, tPHL Propagation delay All PLL bypass 3.6 ns
tr/tf Rise and fall time VDDOUT = 2.5 V (20%–80%) 0.8 ns
tjit(cc) Cycle-to-cycle jitter(2) (3) 1 PLL switching, Y2-to-Y3 50 70 ps
2 PLL switching, Y2-to-Y5 90 130
tjit(per) Peak-to-peak period jitter(3) 1 PLL switching, Y2-to-Y3 60 100 ps
2 PLL switching, Y2-to-Y5 100 160
tsk(o) Output skew(4) fOUT = 50 MHz, Y1-to-Y3 70 ps
fOUT = 50 MHz, Y2-to-Y5 150
odc Output duty cycle(5) fVCO = 100 MHz, Pdiv = 1 45% 55%
CDCEL925 – LVCMOS FOR VDDOUT = 1.8 V
VOH LVCMOS high-level output voltage VDDOUT = 1.7 V, IOH = –0.1 mA 1.6 V
VDDOUT = 1.7 V, IOH = –4 mA 1.4
VDDOUT = 1.7 V, IOH = –8 mA 1.1
VOL LVCMOS low-level output voltage VDDOUT = 1.7 V, IOL = 0.1 mA 0.1 V
VDDOUT = 1.7 V, IOL = 4 mA 0.3
VDDOUT = 1.7 V, IOL = 8 mA 0.6
tPLH, tPHL Propagation delay All PLL bypass 2.6 ns
tr/tf Rise and fall time VDDOUT = 1.8 V (20%–80%) 0.7 ns
tjit(cc) Cycle-to-cycle jitter (2) (3) 1 PLL switching, Y2-to-Y3 80 110 ps
2 PLL switching, Y2-to-Y5 130 200
tjit(per) Peak-to-peak period jitter (3) 1 PLL switching, Y2-to-Y3 100 130 ps
2 PLL switching, Y2-to-Y5 150 220
tsk(o) Output skew (4) fOUT = 50 MHz, Y1-to-Y3 50 ps
fOUT = 50 MHz, Y2-to-Y5 110
odc Output duty cycle (5) fVCO = 100 MHz, Pdiv = 1 45% 55%
SDA AND SCL
VIK SCL and SDA input clamp voltage VDD = 1.7 V, II = –18 mA –1.2 V
IIH SCL and SDA input current VI = VDD, VDD = 1.9 V ±10 µA
VIH SDA/SCL input high voltage(6) 0.7 × VDD V
VIL SDA/SCL input low voltage(6) 0.3 × VDD V
VOL SDA low-level output voltage IOL = 3 mA, VDD = 1.7 V 0.2 × VDD V
CI SCL/SDA Input capacitance VI = 0 V or VDD 3 10 pF
(1) All typical values are at respective nominal VDD.
(2) 10,000 cycles
(3) Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 135 MHz, fOUT = 27 MHz. fOUT = 3.072 MHz or input frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz. fOUT = 16.384 MHz, fOUT = 25 MHz, fOUT = 74.25 MHz, fOUT = 48 MHz
(4) The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider, data sampled on rising edge (tr).
(5) odc depends on output rise- and fall-time (tr/tf);
(6) SDA and SCL pins are 3.3-V tolerant.

7.6 EEPROM Specification

MIN TYP MAX UNIT
EEcyc Programming cycles of EEPROM 100 1000 cycles
EEret Data retention 10 years

7.7 Timing Requirements: CLK_IN

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
fCLK LVCMOS clock input frequency PLL bypass mode 0 160 MHz
PLL mode 8 160
tr / tf Rise and fall time CLK signal (20% to 80%) 3 ns
dutyCLK Duty cycle CLK at VDD / 2 40% 60%

7.8 Timing Requirements: SDA/SCL

over operating free-air temperature range (unless otherwise noted; see Figure 8)
MIN NOM MAX UNIT
fSCL SCL clock frequency Standard mode 0 100 kHz
Fast mode 0 400
tsu(START) START setup time (SCL high before SDA low) Standard mode 4.7 µs
Fast mode 0.6
th(START) START hold time (SCL low after SDA low) Standard mode 4 µs
Fast mode 0.6
tw(SCLL) SCL low-pulse duration Standard mode 4.7 µs
Fast mode 1.3
tw(SCLH) SCL high-pulse duration Standard mode 4 µs
Fast mode 0.6
th(SDA) SDA hold time (SDA valid after SCL low) Standard mode 0 3.45 µs
Fast mode 0 0.9
tsu(SDA) SDA setup time Standard mode 250 ns
Fast mode 100
tr SCL/SDA input rise time Standard mode 1000 ns
Fast mode 300
tf SCL/SDA input fall time, standard and fast mode 300 ns
tsu(STOP) STOP setup time Standard mode 4 µs
Fast mode 0.6
tBUS Bus free time between a STOP and START condition Standard mode 4.7 µs
Fast mode 1.3

7.9 Typical Characteristics

CDCE925 CDCEL925 idd_f_cas847.gif Figure 1. CDCEx925 Supply Current vs PLL Frequency
CDCE925 CDCEL925 iddo2_fo_cas847.gif Figure 3. CDCEL925 Output Current vs Output Frequency
CDCE925 CDCEL925 io_fo_cas847.gif Figure 2. CDCE925 Output Current vs Output Frequency