SCAS918E June   2013  – August 2024 CDCE913-Q1 , CDCEL913-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Control Terminal Configuration
      2. 8.3.2 Default Device Configuration
      3. 8.3.3 I2C Serial Interface
      4. 8.3.4 Data Protocol
    4. 8.4 Device Functional Modes
      1. 8.4.1 SDA and SCL Hardware Interface
    5. 8.5 Programming
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Spread-Spectrum Clock (SSC)
        2. 9.2.2.2 PLL Frequency Planning
        3. 9.2.2.3 Crystal Oscillator Start-Up
        4. 9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 9.2.2.5 Unused Inputs and Outputs
        6. 9.2.2.6 Switching Between XO and VCXO Mode
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Register Maps
    1. 10.1 I2C Configuration Registers
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Revision History

Changes from Revision D (February 2024) to Revision E (August 2024)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Included links to Applications listGo
  • Updated footnote language to conform to updated TI Datasheet Guidelines through the Specifications sectionGo
  • Updated Power Supply Recommendations section with correct power sequenceGo

Changes from Revision C (November 2016) to Revision D (February 2024)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Added Functional Safety information for the CDCE913-Q1Go
  • Changed all instances of legacy terminology to controller and target where I2C is mentioned.Go
  • Changed Device Information table to Package Information Go
  • Removed the thermal pad from the TSSOP pinoutGo
  • Added Y1 to Y3 cycle-to-cycle jitter and Peak-to-peak period jitter specs with tablenotes explaining the configuration differences Go
  • Deleted sentence - A different default setting can be programmed upon customer request. Contact Texas Instruments sales or marketing representative for more information.Go
  • Changed units from kbit/s to kbpsGo
  • Added information on allowable data inputs during the EEPROM write cycle in Data Protocol Go

Changes from Revision B (September 2016) to Revision C (November 2016)

  • Clarified different temperature range for the CDCEL913-Q1 device.Go

Changes from Revision A (June 2013) to Revision B (September 2016)

  • Added Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.Go
  • Changed ESD Ratings: Human-body model (HBM) from 2500 V to 2000 V and Charged-device model (CDM) from 500 V to 1000 V.Go
  • Changed second S to Sr in Byte Read Protocol.Go

Changes from Revision * (June 2013) to Revision A (June 2013)

  • Changed CDM ESD classification level.Go
  • Added ESD ratings.Go
  • Changed IDDPD typical From: 20 To: 30Go
  • Changed II LVCMOS input current value from typical to maximum.Go
  • Changed IIH LVCMOS input current for S0, S1, and S2 value from typical to maximum.Go
  • Changed IIL LVCMOS input current for S0, S1, and S2 value from typical to maximum.Go
  • Changed Test Load for 50-Ω Board Environment.Go
  • Changed Output Selection From: (Y2, Y9) To: (Y2, Y3).Go
  • Changed text note for Block Write Protocol.Go
  • Changed 01h, Bit 7 From: For internal use – always write 1 To: Reserved – always write 0.Go
  • Changed 06h, 7:1 From: 30h To: 20hGo