SLPS598E May   2017  – June 2024 CSD88584Q5DC

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Recommended Operating Conditions
    3. 4.3 Power Block Performance
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Typical Power Block Device Characteristics
    7. 4.7 Typical Power Block MOSFET Characteristics
  6. 5Application and Implementation
    1. 5.1 Application Information
    2. 5.2 Brushless DC Motor With Trapezoidal Control
    3. 5.3 Power Loss Curves
    4. 5.4 Safe Operating Area (SOA) Curve
    5. 5.5 Normalized Power Loss Curves
    6. 5.6 Design Example – Regulate Current to Maintain Safe Operation
    7. 5.7 Design Example – Regulate Board and Case Temperature to Maintain Safe Operation
      1. 5.7.1 Operating Conditions
      2. 5.7.2 Calculating Power Loss
      3. 5.7.3 Calculating SOA Adjustments
  7. 6Layout
    1. 6.1 Layout Guidelines
      1. 6.1.1 Electrical Performance
      2. 6.1.2 Thermal Considerations
    2. 6.2 Layout Example
  8. 7Device and Documentation Support
    1. 7.1 Receiving Notification of Documentation Updates
    2. 7.2 Support Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1.2 Thermal Considerations

The CSD88584Q5DC power block device has the ability to utilize the PCB copper planes as the primary thermal path. As such, the use of thermal vias included in the footprint is an effective way to pull away heat from the device and into the system board. Concerns regarding solder voids and manufacturability issues can be addressed through the use of three basic tactics to minimize the amount of solder attach that will wick down the via barrel:

  • Intentionally space out the vias from one another to avoid a cluster of holes in a given area.
  • Use the smallest drill size allowed by the design. The example in Figure 6-2 uses vias with a 10mil drill hole and a 16mil solder pad.
  • Tent the opposite side of the via with solder-mask. Ultimately the number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturing capabilities.

To take advantage of the DualCool thermally enhanced package, an external heatsink can be applied on top of the power block devices. For low EMI, the heatsink is usually connected to GND through the mounting screws to the PCB. Gap pad insulators with good thermal conductivity should be used between the top of the package and the heatsink. The Bergquist Sil-Pad 980 is recommended which provides excellent thermal impedance of 1.07°C/W at 50psi.