SLPS416C June   2014  – March 2015 CSD95372AQ5M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Power Stage Characteristics
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Functional Description
      1. 7.2.1 Powering the CSD95372AQ5M and Gate Drivers
      2. 7.2.2 Undervoltage Lockout (UVLO) Protection
      3. 7.2.3 ENABLE
      4. 7.2.4 Power Up Sequencing
      5. 7.2.5 PWM
      6. 7.2.6 FCCM
      7. 7.2.7 TAO/FAULT (Thermal Analog Output/Protection Flag)
      8. 7.2.8 Over Temperature
      9. 7.2.9 Gate Drivers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Power Loss Curves
    3. 8.3 Safe Operating Curves (SOA)
    4. 8.4 Normalized Curves
    5. 8.5 Calculating Power Loss and SOA
      1. 8.5.1 Design Example
      2. 8.5.2 Calculating Power Loss
      3. 8.5.3 Calculating SOA Adjustments
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Recommended Schematic Overview
      2. 9.1.2 Recommended PCB Design Overview
        1. 9.1.2.1 Electrical Performance
        2. 9.1.2.2 Thermal Performance
      3. 9.1.3 Sensing Performance
    2. 9.2 Layout Example
  10. 10Application Schematic
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Drawing
    2. 12.2 Recommended PCB Land Pattern
    3. 12.3 Recommended Stencil Opening

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DQP|12
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Layout

9.1 Layout Guidelines

9.1.1 Recommended Schematic Overview

There are several critical components that must be used in conjunction with this Power Stage device. Figure 16 shows a portion of a schematic with the critical components needed for proper operation.

  • C1: Bootstrap Capacitor
  • R1: Bootstrap Resistor
  • C4: Bypass Capacitor for TAO
  • C3: Bypass Capacitor for VDD
  • C5: Bypass Capacitor for VIN to Help with Ringing Reduction
  • C6: Bypass Capacitor for VIN

CSD95372AQ5M Circuit_Schematic.pngFigure 16. Recommended Schematic

9.1.2 Recommended PCB Design Overview

There are two key system-level parameters that can be addressed with a proper PCB design: electrical and thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. Below is a brief description on how to address each parameter.

9.1.2.1 Electrical Performance

The CSD95372AQ5M has the ability to switch at voltage rates greater than 10 kV/µs. Special care must be then taken with the PCB layout design and placement of the input capacitors, inductor and output capacitors.

  • The placement of the input capacitors relative to VIN and PGND pins of CSD95372AQ5M device should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 17). The example in Figure 17 uses 1 x 3.3 nF 0402 50 V and 6 x 10 µF 1206 25 V ceramic capacitors (TDK part number C3216X7R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the Power Stage C5, C8 and C6, C19 should follow in order.
  • The bootstrap cap CBOOT 0.1 µF 0603 16 V ceramic capacitor should be closely connected between BOOT and BOOT_R pins
  • The switching node of the output inductor should be placed relatively close to the Power Stage CSD95372AQ5M VSW pins. Minimizing the VSW node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level. (1)
(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla

9.1.2.2 Thermal Performance

The CSD95372AQ5M has the ability to use the GND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that will wick down the via barrel:

  • Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
  • Use the smallest drill size allowed in your design. The example in Figure 17 uses vias with a 10 mil drill hole and a 26 mil capture pad.
  • Tent the opposite side of the via with solder-mask.

In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturing capabilities.

9.1.3 Sensing Performance

The integrated temperature sensing technology built in the driver of the CSD95372AQ5M produces an analog signal that is proportional to the temperature of the lead-frame of the device, which is almost identical to the junction temperature of the Sync FET. To calculate the junction temperature based on the TAO voltage, use Equation 2. TAO should be bypassed to PGND with a 1 nF X7R ceramic capacitor for optimal performance. The TAO pin has limited sinking current capability in order to enable several power stages that are wire OR-ed together to report only the highest temperature (or fault condition if present). In order to ensure accurate temperature reporting, the TAO nets should be routed on a quiet inner layer between ground planes where possible. In addition, the TAO bypass capacitor should have a PGND pour on the layer directly beneath to ensure proper decoupling. The TAO net should always be shielded from VSW and VIN whenever possible.

Equation 2. TJ[C°] = (TAO[mV] - 400[mV]) / 8[mV/°C]

9.2 Layout Example

CSD95372AQ5M Recommended_Circuit_Layout_slps416.gifFigure 17. Recommended PCB Layout (Top Down View)