SLPS416C June   2014  – March 2015 CSD95372AQ5M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Power Stage Characteristics
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Functional Description
      1. 7.2.1 Powering the CSD95372AQ5M and Gate Drivers
      2. 7.2.2 Undervoltage Lockout (UVLO) Protection
      3. 7.2.3 ENABLE
      4. 7.2.4 Power Up Sequencing
      5. 7.2.5 PWM
      6. 7.2.6 FCCM
      7. 7.2.7 TAO/FAULT (Thermal Analog Output/Protection Flag)
      8. 7.2.8 Over Temperature
      9. 7.2.9 Gate Drivers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Power Loss Curves
    3. 8.3 Safe Operating Curves (SOA)
    4. 8.4 Normalized Curves
    5. 8.5 Calculating Power Loss and SOA
      1. 8.5.1 Design Example
      2. 8.5.2 Calculating Power Loss
      3. 8.5.3 Calculating SOA Adjustments
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Recommended Schematic Overview
      2. 9.1.2 Recommended PCB Design Overview
        1. 9.1.2.1 Electrical Performance
        2. 9.1.2.2 Thermal Performance
      3. 9.1.3 Sensing Performance
    2. 9.2 Layout Example
  10. 10Application Schematic
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Drawing
    2. 12.2 Recommended PCB Land Pattern
    3. 12.3 Recommended Stencil Opening

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DQP|12
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings(1)

TA = 25°C (unless otherwise noted)
MIN MAX UNIT
VIN to PGND –0.3 25 V
VSW to PGND –0.3 25 V
VSW to PGND (<10 ns) –7 27 V
VDD to PGND –0.3 7 V
ENABLE, PWM, FCCM, TAO to PGND(2) –0.3 VDD + 0.3 V
BOOT to BOOT_R(2) –0.3 VDD + 0.3 V
PD, Power Dissipation 12 W
TJ, Operating Temperature Range –55 150 °C
Tstg, Storage Temperature Range –55 150 °C
(1) Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability.
(2) Should not exceed 7 V.

6.2 ESD Ratings

VALUE UNIT
ESD Rating Human Body Model (HBM) ±2000 V
Charged Device Model (CDM) ±500

6.3 Recommended Operating Conditions

TA = 25° (unless otherwise noted)
MIN MAX UNIT
VDD Gate Drive Voltage 4.5 5.5 V
VIN Input Supply Voltage 16 V
VOUT Output Voltage 5.5 V
IOUT Continuous Output Current VIN = 12 V, VDD = 5 V, VOUT = 1.8 V,
ƒSW = 500 kHz, LOUT = 0.22 µH(1)		 60 A
IOUT-PK Peak Output Current(2) 90 A
ƒSW Switching Frequency CBST = 0.1 µF (min) 2000 kHz
On Time Duty Cycle ƒSW = 1 MHz 85 %
Minimum PWM On Time 20 ns
Operating Temperature –40 125 °C
(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(2) System conditions as defined in Note 1. Peak Output Current is applied for tp = 50 µs.

6.4 Thermal Information

TA = 25°C (unless otherwise noted)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-Case Thermal Resistance (Top of package)(1) 15 °C/W
RθJB Junction-to-Board Thermal Resistance(2) 2
(1) RθJC is determined with the device mounted on a 1 inch² (6.45 cm²), 2 oz (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches, 0.06 inch (1.52 mm) thick FR4 board.
(2) RθJB value based on hottest board temperature within 1 mm of the package.

6.5 Electrical Characteristics

TA = 25°C, VDD = POR to 5.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PLOSS
Power Loss(1) VIN = 12 V, VDD = 5 V, VOUT = 1.2 V, IOUT = 30 A,
ƒSW = 500 kHz, LOUT = 0.22 µH , TJ = 25°C		 3.3 W
Power Loss(2) VIN = 12 V, VDD = 5 V, VOUT = 1.2 V, IOUT = 30 A,
ƒSW = 500 kHz, LOUT = 0.22 µH , TJ = 125°C		 3.9 W
VIN
IQ VIN Quiescent Current ENABLE = 0, VDD = 5 V 10 µA
VDD
IDD Standby Supply Current ENABLE = 0, PWM = 0 250 µA
IDD Operating Supply Current ENABLE = 5 V, PWM = 50% Duty cycle,
ƒSW = 500 kHz		 23 mA
POWER-ON RESET AND UNDERVOLTAGE LOCKOUT
VDD Rising Power-On Reset 3.9 V
VDD Falling UVLO 3.4 V
Hysteresis 100 250 mV
Startup Delay(3) ENABLE = 5 V 6 µs
ENABLE
VIH Logic Level High Schmitt Trigger Input
See Figure 11		 2.0 V
VIL Logic Level Low 0.8 V
Weak Pulldown Impedance 100 kΩ
tPDH Rising Propagation Delay 3 µs
tPDL Falling Propagation Delay 30 ns
FCCM
VIH Logic Level High Schmitt Trigger Input
See Figure 13 and Figure 14		 2.0 V
VIL Logic Level Low 0.8 V
Weak Pullup Current 5 µA
THERMAL SHUTDOWN(2)
Start Threshold 150 165 °C
Temperature Hysteresis 25 °C
PWM
IPWMH PWM = 5 V 500 µA
IPWML PWM = 0 –500 µA
VPWMH PWM Logic Level High CPWM = 10 pF 2.3 2.5 2.7 V
VPWML PWM Logic Level Low 0.7 0.9 1.1 V
PWM Tri-State Open Voltage 1.5 V
tPDLH and tPDHL PWM to VSW Propagation Delay(2) 50 ns
t3HT Tri-State Shutdown Hold-off Time (2) 30 ns
t3SD Tri-State Shutdown Propagation Delay(2) 80 160 ns
t3RD Tri-State Recovery Propagation Delay(2) 50 80 ns
tDEM Diode Emulation Minimum On Time(2) 150 ns
BOOTSTRAP SWITCH
VFBOOT Forward Voltage Measured from VDD to VBOOT, IF = 10 mA 200 360 mV
IRBOOT Reverse Leakage(1) VBOOT – VDD = 20 V 0.15 1 µA
ZERO CROSSING COMPARATOR
LS FET Turn-off Current Diode Emulation Mode Enabled
VOUT = 1.8 V, L = 150 nH		 0 1.125 A
THERMAL ANALOG OUTPUT TAO
Output Voltage at 25°C 0.56 0.60 0.64 V
Output Voltage Temperature Coefficient 8 mV/°C
(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(2) Specified by design
(3) POR to VSW Rising

6.6 Typical Power Stage Characteristics

TJ = 125°C, unless stated otherwise. The typical CSD95372A system characteristic curves are based on measurements made on a PCB design with dimensions of 4 inches (W) x 3.5 inches (L) x 0.062 inch (T) and 6 copper layers of 1 oz. copper thickness. See the Application Information section for a detailed explanation.
CSD95372AQ5M graph01_f2_slps416.png
Figure 1. Power Loss vs Output Current
CSD95372AQ5M graph03h_f2_slps416.png
Figure 3. Safe Operating Area – PCB Horizontal Mount (1)
CSD95372AQ5M graph06_f2_slps416.png
Figure 5. Normalized Power Loss vs Frequency
CSD95372AQ5M graph08_f3_slps416.png
Figure 7. Normalized Power Loss vs Output Voltage
CSD95372AQ5M graph10_f2_slps416.png
Figure 9. Driver Current vs Frequency
CSD95372AQ5M graph02_f2_slps416.png
Figure 2. Power Loss vs Temperature
CSD95372AQ5M graph05_f2_slps416.png
Figure 4. Typical Safe Operating Area (1)
CSD95372AQ5M graph07_f3_slps416.png
Figure 6. Normalized Power Loss vs Input Voltage
CSD95372AQ5M graph09_f_slps416.png
A.
Figure 8. Normalized Power Loss vs Output Inductance