SLASFK2 December   2024 DAC121S101-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 DAC Section
      2. 6.3.2 Resistor String
      3. 6.3.3 Output Amplifier
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-On Reset
      2. 6.4.2 Power-Down Modes
    5. 6.5 Programming
      1. 6.5.1 Serial Interface
      2. 6.5.2 Input Shift Register
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Bipolar Operation
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGK|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4.2 Power-Down Modes

Table 6-1 lists the DAC121S101-SEP four modes of operation. These modes are set with two bits (DB13 and DB12) in the control register.

Table 6-1 Modes of Operation
DB13 DB12 OPERATING MODE
0 0 Normal operation
0 1 Power-down with 1kΩ to GND
1 0 Power-down with 100kΩ to GND
1 1 Power-down with Hi-Z

When both DB13 and DB12 are 0, the device operates normally. For the other three possible combinations of these bits the supply current drops to the power-down level and the output is pulled down with either a 1kΩ or a 100kΩ resistor, or is in a high-impedance state, as described in Table 6-1.

The bias generator, output amplifier, the resistor string and other linear circuitry are shut down in any of the power-down modes. However, the contents of the DAC register are unaffected when in power-down; therefore, when coming out of power down, the output voltage returns to the same voltage before entering power down. Minimum power consumption is achieved in the power-down mode with SCLK disabled and SYNC and DIN idled low. The time to exit power-down (the wake-up time) is typically tWU (µs) as stated in the Dynamic Performance section of the Electrical Characteristics table.