The three-wire interface is compatible with SPI, QSPI and MICROWIRE, as well as most DSPs. See Figure 5-1 for information on a write sequence.

A write sequence begins by bringing the SYNC line low. After SYNC is low, the data on the DIN line is clocked into the 16-bit serial input register on the falling edges of SCLK. On the 16th falling clock edge, the last data bit is clocked in, and the programmed function (a change in the mode of operation, a change in the DAC register contents, or both) is executed. At this point, the SYNC line can be kept low or brought high. In either case, bring the SYNC line high for the minimum specified time before the next write sequence because a falling edge of SYNC can initiate the next write cycle.

The SYNC and DIN buffers draw more current when high; therefore, idle these buffers low between write sequences to minimize power consumption.