SLASFK2 December   2024 DAC121S101-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 DAC Section
      2. 6.3.2 Resistor String
      3. 6.3.3 Output Amplifier
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-On Reset
      2. 6.4.2 Power-Down Modes
    5. 6.5 Programming
      1. 6.5.1 Serial Interface
      2. 6.5.2 Input Shift Register
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Bipolar Operation
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGK|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Timing Requirements

all input signals are specified at 2.7V ≤ VA ≤ 5.5V, TA = 25°C, and  fSCLK = 30MHz (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSCLK SCLK frequency(1) 30 MHz
1/fSCLK SCLK cycle time(1) 33 ns
tH SCLK high time(1) 5 ns
tL SCLK low time(1) 5 ns
tSUD DIN setup time(1) 2.5 ns
tDHD DIN hold time(1) 2.5 ns
tSUCL SYNC to SCLK rising edge setup time(1) −15 ns
tCS SCLK falling edge to SYNC rising edge(1) VA = 5V 0 ns
VA = 3V −2
tSYNC SYNC high time(1) 2.7V ≤ VA ≤ 3.6V 9 ns
3.6V ≤ VA ≤ 5.5V 5
(1) Specified by design and characterization, not production tested.