SNAS410F May 2008 – July 2016 DAC121S101QML-SP
PRODUCTION DATA.
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage, VA | 6.5 | V | ||
Voltage on any input pin | −0.3 | (VA + 0.3) | V | |
Input current at any pin(3) | 10 | mA | ||
Maximum output current(4) | 10 | mA | ||
VOUT pin in power-down mode | 1 | mA | ||
Package input current(3) | 20 | mA | ||
Power dissipation at TA = 25°C | See(5) | |||
Maximum junction temperature | 175 | °C | ||
Lead temperature | CFP package (Soldering 10 Seconds) |
260 | °C | |
Package weight (typical) | CFP package | 220 | mg | |
Storage temperature, Tstg | −65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) | ±5000 | V |
MIN | MAX | UNIT | |
---|---|---|---|
Operating temperature | −55 | 125 | °C |
Supply voltage, VA | 2.7 | 5.5 | V |
Any input voltage(1) | −0.1 | (VA + 0.1) | V |
Output load | 0 | 1500 | pF |
SCLK frequency | 20 | MHz |
THERMAL METRIC(1)(2) | DAC121S101QML-SP | UNIT | |
---|---|---|---|
NAC (CFP) | |||
10 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 214 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 25.7 | °C/W |
PARAMETER | TEST CONDITIONS | NOTES | SUB-GROUPS | MIN | TYP(1) | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|---|
STATIC PERFORMANCE | |||||||||
Resolution | TMIN ≤ TA ≤ TMAX | See(2) | 12 | Bits | |||||
Monotonicity | TMIN ≤ TA ≤ TMAX | See(2) | 12 | Bits | |||||
INL | Integral non-linearity | Over Decimal codes 48 to 4047 | [1, 2, 3] | −8 | ±2.75 | 8 | LSB | ||
DNL | Differential non-linearity | VA = 2.7 V to 5.5 V | DNL MAX | [1, 2, 3] | 0.21 | 1 | LSB | ||
DNL MIN | −0.7 | −0.1 | |||||||
ZE | Zero code error | IOUT = 0 | [1, 2, 3] | 2.12 | 15 | mV | |||
FSE | Full-scale error | IOUT = 0 | [1, 2, 3] | −0.04 | −1 | %FSR | |||
GE | Gain error | All ones Loaded to DAC register | [1, 2, 3] | −0.11 | ±1 | %FSR | |||
ZCED | Zero code error drift | See(2) | −20 | µV/°C | |||||
TC GE | Gain error tempco | VA = 3 V | See(2) | −0.7 | ppm/°C | ||||
VA = 5 V | −1 | ||||||||
OUTPUT CHARACTERISTICS | |||||||||
IPD SINK | Vout pin in power-down mode | All PD Modes, TMIN ≤ TA ≤ TMAX | See(2) | 1 | mA | ||||
Output voltage range | TMIN ≤ TA ≤ TMAX | See(2) | 0 | VA | V | ||||
ZCO | Zero code output | VA = 3 V, IOUT = 10 µA | [1, 2, 3] | 2 | 6 | mV | |||
VA = 3 V, IOUT = 100 µA | [1, 2, 3] | 4 | 10 | ||||||
VA = 5 V, IOUT = 10 µA | [1, 2, 3] | 2 | 8 | ||||||
VA = 5 V, IOUT = 100 µA | [1, 2, 3] | 4 | 9 | ||||||
FSO | Full-scale output | VA = 3 V, IOUT = 10 µA | [1, 2, 3] | 2.99 | 2.997 | V | |||
VA = 3 V, IOUT = 100 µA | [1, 2, 3] | 2.985 | 2.991 | ||||||
VA = 5 V, IOUT = 10 µA | [1, 2, 3] | 4.985 | 4.994 | ||||||
VA = 5 V, IOUT = 100 µA | [1, 2, 3] | 4.985 | 4.992 | ||||||
Maximum load capacitance | RL = ∞ | See(2) | 1500 | pF | |||||
RL = 2 kΩ | 1500 | ||||||||
DC output impedance | [1, 2, 3] | 8 | 16 | Ω | |||||
LOGIC INPUT | |||||||||
IIN | Input current | [1, 2, 3] | −200 | 6 | 200 | nA | |||
VIL | Input low voltage | VA = 5 V, TMIN ≤ TA ≤ TMAX | [1, 2, 3] | 0.8 | V | ||||
VA = 3 V, TMIN ≤ TA ≤ TMAX | [1, 2, 3] | 0.5 | |||||||
VIH | Input high voltage | VA = 5 V, TMIN ≤ TA ≤ TMAX | [1, 2, 3] | 2.4 | V | ||||
VA = 3 V, TMIN ≤ TA ≤ TMAX | [1, 2, 3] | 2.1 | |||||||
CIN | Input capacitance | See(2) | 5 | pF | |||||
POWER REQUIREMENTS | |||||||||
IA | Supply current (output unloaded) | Normal Mode 5.5 V fSCLK = 20 MHz |
[1, 2, 3] | 216 | 270 | µA | |||
Normal Mode 3.6 V fSCLK = 20 MHz |
[1, 2, 3] | 145 | 200 | ||||||
Normal Mode 5.5 V fSCLK = 10 MHz |
[1, 2, 3] | 185 | 230 | ||||||
Normal Mode 3.6 V fSCLK = 10 MHz |
[1, 2, 3] | 132 | 175 | ||||||
Normal Mode 5.5 V fSCLK = 0 |
[1, 2, 3] | 150 | 190 | ||||||
Normal Mode 3.6 V fSCLK = 0 |
[1, 2, 3] | 115 | 160 | ||||||
All PD Modes, 5.5 V fSCLK = 20 MHz |
[1, 2, 3] | 22 | 60 | ||||||
All PD Modes, 3.6 V fSCLK = 20 MHz |
[1, 2, 3] | 12 | 30 | ||||||
All PD Modes, 5.5 V fSCLK = 10 MHz |
[1, 2, 3] | 12 | 40 | ||||||
All PD Modes, 3.6 V fSCLK = 10 MHz |
[1, 2, 3] | 6 | 20 | ||||||
All PD Modes, 5.5 V fSCLK = 0 |
[1, 2, 3] | 0.006 | 1 | ||||||
All PD Modes, 3.6 V fSCLK = 0 |
[1, 2, 3] | 0.004 | 1 | ||||||
PC | Power consumption (output unloaded) | Normal Mode, 5.5 V fSCLK = 20 MHz |
[1, 2, 3] | 1.19 | 1.49 | mW | |||
Normal Mode 3.6 V fSCLK = 20 MHz |
[1, 2, 3] | 0.52 | 0.72 | ||||||
Normal Mode, 5.5 V fSCLK = 10 MHz |
[1, 2, 3] | 1.02 | 1.27 | ||||||
Normal Mode 3.6 V fSCLK = 10 MHz |
[1, 2, 3] | 0.47 | 0.63 | ||||||
Normal Mode, 5.5 V fSCLK = 0 |
[1, 2, 3] | 0.82 | 1.05 | ||||||
Normal Mode 3.6 V fSCLK = 0 |
[1, 2, 3] | 0.41 | 0.58 | ||||||
All PD Modes, 5.5 V fSCLK = 20 MHz |
[1, 2, 3] | 0.12 | 0.33 | ||||||
All PD Modes, 3.6 V fSCLK = 20 MHz |
[1, 2, 3] | 0.07 | 0.11 | ||||||
All PD Modes, 5.5 V fSCLK = 10 MHz |
[1, 2, 3] | 0.04 | 0.22 | ||||||
All PD Modes, 3.6 V fSCLK = 10 MHz |
[1, 2, 3] | 0.02 | 0.08 | ||||||
All PD Modes, 5.5 V fSCLK = 0 |
[1, 2, 3] | 0.033 | 5.5 | ||||||
All PD Modes, 3.6 V fSCLK = 0 |
[1, 2, 3] | 0.014 | 3.6 | ||||||
IOUT | Power efficiency | ILOAD = 2 mA | See(2) | 91% | |||||
IA | 94% |
PARAMETER | TEST CONDITIONS | NOTES | SUB-GROUPS | MIN | TYP(1) | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|---|---|
fSCLK | SCLK frequency | (See Figure 31) | [9,10,11] | 20 | MHz | |||||
ts | Output voltage settling time |
FF0 to 00F code change, RL = ∞ | CL ≤ 200 pF | [9,10,11] | 12.5 | 15 | µs | |||
CL = 500 pF | [9,10,11] | 12.5 | 15 | |||||||
00Fh to FF0h code change, RL = ∞ | CL ≤ 200 pF | [9,10,11] | 12.5 | 15 | ||||||
CL = 500 pF | [9,10,11] | 12.5 | 15 | |||||||
SR | Output slew rate | See(2) | 1 | V/µs | ||||||
Glitch impulse | Code change from 800h to 7FFh | See(2) | 12 | nV-sec | ||||||
Digital feedthrough | See(2) | 0.5 | nV-sec | |||||||
tWU | Wake-Up Time | VA = 5 V | See(2) | 0.65 | µs | |||||
VA = 3 V | 1.1 | |||||||||
1/fSCLK | SCLK cycle time | (See Figure 31) | [9,10,11] | 50 | ns | |||||
tH | SCLK high time | (See Figure 31) | [9,10,11] | 20 | ns | |||||
tL | SCLK low time | (See Figure 31) | [9,10,11] | 20 | ns | |||||
tSUCL | Setup time SYNC to SCLK rising edge | (See Figure 31) | [9,10,11] | 0 | ns | |||||
tSUD | Data setup time | (See Figure 31) | [9,10,11] | 6 | ns | |||||
tDHD | Data hold time | (See Figure 31) | [9,10,11] | 4.5 | ns | |||||
tCS | SCLK fall to rise of SYNC | VA = 5.5 V (See Figure 31) | [9,10,11] | 10 | ns | |||||
VA = 2.7 V (See Figure 31) | [9,10,11] | 18 | ||||||||
tSYNC | SYNC high time | VA = 5.5 V (See Figure 31) | [9,10,11] | 37 | ns | |||||
VA = 2.7 V (See Figure 31) | [9,10,11] | 36 |
PARAMETER | TEST CONDITIONS | SUB-GROUPS | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
POWER REQUIREMENTS | |||||||
IA | Supply current (output unloaded) | Normal Mode fSCLK = 20 MHz |
5.5 V | [1] | 325 | µA | |
3.6 V | [1] | 250 | |||||
Normal Mode fSCLK = 10 MHz |
5.5 V | [1] | 300 | ||||
3.6 V | [1] | 225 | |||||
Normal Mode fSCLK = 0 |
5.5 V | [1] | 275 | ||||
3.6 V | [1] | 200 | |||||
All PD Modes, fSCLK = 20 MHz |
5.5 V | [1] | 125 | ||||
3.6 V | [1] | 100 | |||||
All PD Modes, fSCLK = 10 MHz |
5.5 V | [1] | 115 | ||||
3.6 V | [1] | 95 | |||||
All PD Modes, fSCLK = 0 |
5.5 V | [1] | 100 | ||||
3.6 V | [1] | 100 |
PARAMETER | TEST CONDITIONS | SUB-GROUPS | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
INL | Integral non-linearity | [1] | ±2 | LBS | ||
ts | Output voltage settling time | [1] | ±5 | µA | ||
IA | Supply current (output unloaded) | Normal Mode, VA = 5.5 V, fSCLK = 20 MHz | [1] | ±10 | µA | |
Normal Mode, VA = 3.6 V, fSCLK = 20 MHz | [1] | ±6 | ||||
Normal Mode, VA = 5.5 V, fSCLK = 10 MHz | [1] | ±10 | ||||
Normal Mode, VA = 3.6 V, fSCLK = 10 MHz | [1] | ±6 | ||||
Normal Mode, VA = 5.5 V, fSCLK = 0 | [1] | ±8 | ||||
Normal Mode, VA = 3.6 V, fSCLK = 0 | [1] | ±6 | ||||
All PD Modes, VA = 5.5 V, fSCLK = 20 MHz | [1] | ±2 | ||||
All PD Modes, VA = 3.6 V, fSCLK = 20 MHz | [1] | ±1 | ||||
All PD Modes, VA = 5.5 V, fSCLK = 10 MHz | [1] | ±1 | ||||
All PD Modes, VA = 3.6 V, fSCLK = 10 MHz | [1] | ±1 | ||||
All PD Modes, VA = 5.5 V, fSCLK = 0 | [1] | ±0.1 | ||||
All PD Modes, VA = 3.6 V, fSCLK = 0 | [1] | ±0.1 |
The DAC121S101QML-SP operates over the extended temperature range of –55°C to +125°C.
See Radiation Environments for dose rate environment information.
SUB-GROUP | DESCRIPTION | TEMP (°C) |
---|---|---|
1 | Static tests at | +25 |
2 | Static tests at | +125 |
3 | Static tests at | –55 |
4 | Dynamic tests at | +25 |
5 | Dynamic tests at | +125 |
6 | Dynamic tests at | –55 |
7 | Functional tests at | +25 |
8A | Functional tests at | +125 |
8B | Functional tests at | –55 |
9 | Switching tests at | +25 |
10 | Switching tests at | +125 |
11 | Switching tests at | –55 |
12 | Setting time at | +25 |
13 | Setting time at | +125 |
14 | Setting time at | –55 |