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  • DAC12DL3200 up to 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel 12-bit Digital-to-Analog Converter (DAC) with Low-Latency LVDS Interface

    • SBAS649B June   2021  – June 2022 DAC12DL3200

      PRODUCTION DATA  

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  • DAC12DL3200 up to 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel 12-bit Digital-to-Analog Converter (DAC) with Low-Latency LVDS Interface
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - Power Consumption
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 2xRF Mode
      2. 7.3.2 DAC Output Interface
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-scale Current Adjustment
        3. 7.3.2.3 Example Analog Output Interfaces
      3. 7.3.3 LVDS Interface
        1. 7.3.3.1 MODE0: Two LVDS banks per channel
        2. 7.3.3.2 MODE1: One LVDS bank per channel
        3. 7.3.3.3 MODE2: Four LVDS banks, single channel mode
        4. 7.3.3.4 LVDS Interface Input Strobe
        5. 7.3.3.5 FIFO Operation
          1. 7.3.3.5.1 Using FIFO Delay Readback Values
          2. 7.3.3.5.2 FIFO Delay Handling
          3. 7.3.3.5.3 FIFO Delay and NCO Operation
          4. 7.3.3.5.4 FIFO Over/Under Flow Alarming
      4. 7.3.4 Multi-Device Synchronization (SYSREF+/-)
        1. 7.3.4.1 DACCLK Domain Synchronization
        2. 7.3.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      5. 7.3.5 Alarms
    4. 7.4 Device Functional Modes
      1. 7.4.1 Direct Digital Synthesis (DDS) Mode
        1. 7.4.1.1 NCO Gain Scaling
        2. 7.4.1.2 NCO Phase Continuous Operation
        3. 7.4.1.3 Trigger Clock
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Operation
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 SPI Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure with LVDS Input
      2. 8.1.2 Startup Procedure With NCO Operation
      3. 8.1.3 Interface Test Pattern and Timing Verification
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
  11. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • ACF|256
    • MPBGAO1C
  • ALJ|256
    • MPBGAS8B
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • sbas649b_oa
  • sbas649b_pm
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    • Full reading width
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DATA SHEET

DAC12DL3200 up to 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel 12-bit Digital-to-Analog Converter (DAC) with Low-Latency LVDS Interface

1 Features

  • 12-bit resolution
  • Maximum input and output sample rate:
    • Single channel up to 6.4 GSPS
    • Dual channel up to 3.2 GSPS
  • Multi-Nyquist operating modes:
    • Single channel modes: NRZ, RTZ, RF
    • Dual channel modes: NRZ, RTZ, RF, 2xRF
  • Low latency through device: 6 to 8 ns
  • Matching transmit capabilities to the low latency receiver ADC12DL3200
    • DAC and ADC combined latency < 15 ns (not including FPGA)
  • Parallel DDR LVDS interface:
    • Source synchronous interface to simplify timing:
    • 24 or 48 LVDS pairs up to 1.6 Gbps
    • 1 LVDS DDR clock per 12-bit bus
  • Output frequency range: > 8 GHz
  • Full-scale current: 21 mA
  • Simplified clocking and synchronization
    • SYSREF windowing eases setup and hold times
  • On-chip direct digital synthesizer (DDS)
    • Single-tone and two-tone sine wave generation
    • 32 x 32-bit numerically controlled oscillators
    • Fast frequency hopping capability (< 500 ns)
    • Synchronous CMOS frequency/phase input
  • Performance at fOUT = 4.703 GHz, 6.4 GSPS, RF mode
    • Output power: –3 dBm
    • Noise floor (70 MHz offset): –147 dBc/Hz
    • SFDR: 60 dBc
  • Power supplies: 1.0 V, 1.8 V, –1.8 V
  • Power consumption: 1.49 W (2-ch, RF mode, 3.2 GSPS)
  • Package: 256-Ball FCBGA (17x17 mm, 1 mm pitch)

2 Applications

  • Electronic warfare
  • Generator: pulse, pattern and arbitrary waveform (AWG)

3 Description

The DAC12DL3200 is a very low latency, dual channel, RF sampling digital-to-analog converter (DAC) capable of input and output rates of up to 3.2-GSPS in dual channel mode or 6.4-GSPS in single channel mode. The DAC can transmit signal bandwidths beyond 2 GHz at carrier frequencies approaching 8 GHz when using the multi-Nyquist output modes. The high output frequency range enables direct sampling through C-band (8 GHz) and beyond.

The DAC12DL3200 can be used as an I/Q baseband DAC in dual channel mode. The high sampling rate and output frequency range also makes the DAC12DL3200 capable of arbitrary waveform generation (AWG) and direct digital synthesis (DDS). An integrated DDS block enables single tone and two tone generation on chip.

The DAC12DL3200 has a parallel LVDS interface that consists of up to 48 LVDS pairs and 4 DDR LVDS clocks. A strobe signal is used to synchronize the interface which can be sent over the least significant bit (LSB) or optionally over dedicated strobe LVDS lanes. Each LVDS pair is capable of up to 1.6 Gbps. Multi-device synchronization is supported using a synchronization signal (SYSREF) and is compatible with JESD204B/C clocking devices. SYSREF windowing eases synchronization in multi-device systems.

Package Information
PART NUMBERPACKAGE(1)BODY SIZE (NOM)
DAC12DL3200FCBGA (256)17 mm x 17 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-2BC84087-3159-4BE1-93EA-18AEE99D3FC2-low.gif Dual Channel Mode Frequency Response

4 Revision History

Changes from Revision A (October 2021) to Revision B (June 2022)

  • Added the Trigger Clock sectionGo
  • Deleted text Streaming mode can be disabled by setting the ADDR_HOLD bit from the Streaming Mode sectionGo
  • Changed the description of Bit 2 in #GUID-662EAAC6-CE6A-4E4E-BAEA-69F89D19D512/GUID-93586D33-A1E8-49EE-982B-A40301284950 Go
  • Changed the description of Bit 1 in #GUID-662EAAC6-CE6A-4E4E-BAEA-69F89D19D512/GUID-9CBC93AB-DFA6-433D-9E5A-ABB7CD618BB2 Go

Changes from Revision * (June 2021) to Revision A (October 2021)

  • Changed the document from Advanced Information to Production dataGo

 
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