DAC12DL3200 up to 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel 12-bit Digital-to-Analog Converter (DAC) with Low-Latency LVDS Interface
- SBAS649B June 2021 – June 2022 DAC12DL3200
  
  PRODUCTION DATA

DATA SHEET

DAC12DL3200 up to 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel 12-bit Digital-to-Analog Converter (DAC) with Low-Latency LVDS Interface

1 Features

12-bit resolution
Maximum input and output sample rate:
- Single channel up to 6.4 GSPS
- Dual channel up to 3.2 GSPS
Multi-Nyquist operating modes:
- Single channel modes: NRZ, RTZ, RF
- Dual channel modes: NRZ, RTZ, RF, 2xRF
Low latency through device: 6 to 8 ns
Matching transmit capabilities to the low latency receiver ADC12DL3200
- DAC and ADC combined latency < 15 ns (not including FPGA)
Parallel DDR LVDS interface:
- Source synchronous interface to simplify timing:
- 24 or 48 LVDS pairs up to 1.6 Gbps
- 1 LVDS DDR clock per 12-bit bus
Output frequency range: > 8 GHz
Full-scale current: 21 mA
Simplified clocking and synchronization
- SYSREF windowing eases setup and hold times
On-chip direct digital synthesizer (DDS)
- Single-tone and two-tone sine wave generation
- 32 x 32-bit numerically controlled oscillators
- Fast frequency hopping capability (< 500 ns)
- Synchronous CMOS frequency/phase input
Performance at f_OUT = 4.703 GHz, 6.4 GSPS, RF mode
- Output power: –3 dBm
- Noise floor (70 MHz offset): –147 dBc/Hz
- SFDR: 60 dBc
Power supplies: 1.0 V, 1.8 V, –1.8 V
Power consumption: 1.49 W (2-ch, RF mode, 3.2 GSPS)
Package: 256-Ball FCBGA (17x17 mm, 1 mm pitch)