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High-speed DACs (>10 MSPS)

DAC12DL3200

ACTIVE

12-bit, low-latency, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling DAC (LVDS interface)

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Data sheet

DAC12DL3200

ACTIVE
Data sheet Order now

Product details

Resolution (Bits) 12 Number of DAC channels 1, 2 Interface type DDR LVDS, Parallel LVDS Sample/update rate (Msps) 3200, 6400 Features Ultra High Speed Rating Catalog Interpolation 1x Power consumption (typ) (mW) 1400 SFDR (dB) 80 Architecture Current Source Operating temperature range (°C) -40 to 85 Reference type Ext, Int
Resolution (Bits) 12 Number of DAC channels 1, 2 Interface type DDR LVDS, Parallel LVDS Sample/update rate (Msps) 3200, 6400 Features Ultra High Speed Rating Catalog Interpolation 1x Power consumption (typ) (mW) 1400 SFDR (dB) 80 Architecture Current Source Operating temperature range (°C) -40 to 85 Reference type Ext, Int
FCBGA (ACF) 256 289 mm² 17 x 17 FCBGA (ALJ) 256 289 mm² 17 x 17
  • 12-bit resolution
  • Maximum input and output sample rate:
    • Single channel up to 6.4 GSPS
    • Dual channel up to 3.2 GSPS
  • Multi-Nyquist operating modes:
    • Single channel modes: NRZ, RTZ, RF
    • Dual channel modes: NRZ, RTZ, RF, 2xRF
  • Low latency through device: 6 to 8 ns
  • Matching transmit capabilities to the low latency receiver ADC12DL3200
    • DAC and ADC combined latency < 15 ns (not including FPGA)
  • Parallel DDR LVDS interface:
    • Source synchronous interface to simplify timing:
    • 24 or 48 LVDS pairs up to 1.6 Gbps
    • 1 LVDS DDR clock per 12-bit bus
  • Output frequency range: > 8 GHz
  • Full-scale current: 21 mA
  • Simplified clocking and synchronization
    • SYSREF windowing eases setup and hold times
  • On-chip direct digital synthesizer (DDS)
    • Single-tone and two-tone sine wave generation
    • 32 x 32-bit numerically controlled oscillators
    • Fast frequency hopping capability (< 500 ns)
    • Synchronous CMOS frequency/phase input
  • Performance at fOUT = 4.703 GHz, 6.4 GSPS, RF mode
    • Output power: –3 dBm
    • Noise floor (70 MHz offset): –147 dBc/Hz
    • SFDR: 60 dBc
  • Power supplies: 1.0 V, 1.8 V, –1.8 V
  • Power consumption: 1.49 W (2-ch, RF mode, 3.2 GSPS)
  • Package: 256-Ball FCBGA (17x17 mm, 1 mm pitch)
  • 12-bit resolution
  • Maximum input and output sample rate:
    • Single channel up to 6.4 GSPS
    • Dual channel up to 3.2 GSPS
  • Multi-Nyquist operating modes:
    • Single channel modes: NRZ, RTZ, RF
    • Dual channel modes: NRZ, RTZ, RF, 2xRF
  • Low latency through device: 6 to 8 ns
  • Matching transmit capabilities to the low latency receiver ADC12DL3200
    • DAC and ADC combined latency < 15 ns (not including FPGA)
  • Parallel DDR LVDS interface:
    • Source synchronous interface to simplify timing:
    • 24 or 48 LVDS pairs up to 1.6 Gbps
    • 1 LVDS DDR clock per 12-bit bus
  • Output frequency range: > 8 GHz
  • Full-scale current: 21 mA
  • Simplified clocking and synchronization
    • SYSREF windowing eases setup and hold times
  • On-chip direct digital synthesizer (DDS)
    • Single-tone and two-tone sine wave generation
    • 32 x 32-bit numerically controlled oscillators
    • Fast frequency hopping capability (< 500 ns)
    • Synchronous CMOS frequency/phase input
  • Performance at fOUT = 4.703 GHz, 6.4 GSPS, RF mode
    • Output power: –3 dBm
    • Noise floor (70 MHz offset): –147 dBc/Hz
    • SFDR: 60 dBc
  • Power supplies: 1.0 V, 1.8 V, –1.8 V
  • Power consumption: 1.49 W (2-ch, RF mode, 3.2 GSPS)
  • Package: 256-Ball FCBGA (17x17 mm, 1 mm pitch)

The DAC12DL3200 is a very low latency, dual channel, RF sampling digital-to-analog converter (DAC) capable of input and output rates of up to 3.2-GSPS in dual channel mode or 6.4-GSPS in single channel mode. The DAC can transmit signal bandwidths beyond 2 GHz at carrier frequencies approaching 8 GHz when using the multi-Nyquist output modes. The high output frequency range enables direct sampling through C-band (8 GHz) and beyond.

The DAC12DL3200 can be used as an I/Q baseband DAC in dual channel mode. The high sampling rate and output frequency range also makes the DAC12DL3200 capable of arbitrary waveform generation (AWG) and direct digital synthesis (DDS). An integrated DDS block enables single tone and two tone generation on chip.

The DAC12DL3200 has a parallel LVDS interface that consists of up to 48 LVDS pairs and 4 DDR LVDS clocks. A strobe signal is used to synchronize the interface which can be sent over the least significant bit (LSB) or optionally over dedicated strobe LVDS lanes. Each LVDS pair is capable of up to 1.6 Gbps. Multi-device synchronization is supported using a synchronization signal (SYSREF) and is compatible with JESD204B/C clocking devices. SYSREF windowing eases synchronization in multi-device systems.

The DAC12DL3200 is a very low latency, dual channel, RF sampling digital-to-analog converter (DAC) capable of input and output rates of up to 3.2-GSPS in dual channel mode or 6.4-GSPS in single channel mode. The DAC can transmit signal bandwidths beyond 2 GHz at carrier frequencies approaching 8 GHz when using the multi-Nyquist output modes. The high output frequency range enables direct sampling through C-band (8 GHz) and beyond.

The DAC12DL3200 can be used as an I/Q baseband DAC in dual channel mode. The high sampling rate and output frequency range also makes the DAC12DL3200 capable of arbitrary waveform generation (AWG) and direct digital synthesis (DDS). An integrated DDS block enables single tone and two tone generation on chip.

The DAC12DL3200 has a parallel LVDS interface that consists of up to 48 LVDS pairs and 4 DDR LVDS clocks. A strobe signal is used to synchronize the interface which can be sent over the least significant bit (LSB) or optionally over dedicated strobe LVDS lanes. Each LVDS pair is capable of up to 1.6 Gbps. Multi-device synchronization is supported using a synchronization signal (SYSREF) and is compatible with JESD204B/C clocking devices. SYSREF windowing eases synchronization in multi-device systems.
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* Data sheet DAC12DL3200 up to 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel 12-bit Digital-to-Analog Converter (DAC) with Low-Latency LVDS Interface datasheet (Rev. B) PDF | HTML 27 Jun 2022
User guide DAC12DL3200 Evaluation Module User's Guide (Rev. A) PDF | HTML 23 May 2022

Design & development

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Evaluation board

DAC12DL3200EVM — DAC12DL3200 evaluation module for 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling DAC

The DAC12DL3200 evaluation module (EVM) is a platform for evaluating the DAC12DL3200, which is a very-low-latency, dual-channel, 12-bit, RF-sampling digital-to-analog converter (DAC), capable of operating at sampling rates up to 3.2 GSPS in dual-channel mode or 6.4 GSPS in single-channel mode.

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User guide: PDF | HTML
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Simulation model

DAC12DL3200 IBIS Model

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PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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FCBGA (ACF) 256 Ultra Librarian
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