DAC12DL3200 Evaluation Module

Abstract

The DAC12DL3200 evaluation module (EVM) is used to evaluate the DAC12DL3200 digital-to-analog converter (DAC) from Texas Instruments. Throughout this document, the terms evaluation board, evaluation module, and EVM are synonymous with the DAC12DL3200EVM.

Trademarks

Microsoft® and Windows® are registered trademarks of Microsoft Corporation.

Rohde & Schwarz® is a registered trademark of Rohde & Schwarz GmbH & Co.

All trademarks are the property of their respective owners.

1 Introduction

The DAC12DL3200 is a very low latency, dual-channel, 12-bit RF sampling digital-to-analog converter (DAC), capable of operating at sampling rates up to 3.2 Giga-samples per second (GSPS) in dual-channel mode, or 6.4 GSPS in single-channel mode. The DAC can transmit signal bandwidths beyond 2 GHz at carrier frequencies approaching 8 GHz when using multi-Nyquist output modes. The DAC12DL3200EVM device input data is transmitted over a high-speed LVDS interface. This evaluation board also includes the following important features:

Transformer-coupled output allowing for a single-ended 50-Ω output signal up to 8 GHz
The LMX2592 clock synthesizer as an option to generate the DAC sampling clock
Transformer-coupled input clock option (board default setup) for quick setup with external clock sources
LMK04828 clock synthesizer for DAC SYSREF and FPGA reference clock source
Device register programming through USB connector and FTDI USB-to-SPI bus translator
High-speed LVDS data input over a 400-pin FMC interface connector

Figure 1-1 DAC12DL3200EVM

The TI TSW14DL3200EVM pattern generator, when used with the TI High-Speed-Data-Converter (HSDC) Pro Software GUI, is used to send LVDS data test patterns to the DAC12DL3200EVM.

With proper hardware selection in the HSDC Pro software, the TSW14DL3200EVM is automatically configured to support the different modes of operation of the DAC12DL3200. The interface provides LVDS output data up to 1600 MSPS.

1.1 Low Latency Evaluation of Receive and Transmit

The TSW14DL3200EVM is designed for plug-and-play evaluation with the DAC12DL3200EVM and ADC12DL3200EVM. This provides a capability for prototyping or testing a low-latency LVDS-based DAC transmitter or ADC receiver, or both simultaneously.

TI takes two approaches for measuring the overall end-to-end latency of the DAC12DL3200 device.

Approach 1: Figure 1-2 illustrates this approach where the test signal is fed into the front end of the ADC12DL3200 device and the samples are extracted and collected by the FPGA. These samples are then forwarded to the DAC12DL3200 which generates the resultant output signal (delayed version of the input test signal). The IO architecture of the Xilinx UltraScale enables extremely high-speed data rates by trading off latency for throughput. At bit-rates over 1.2Gbps, the SERDES blocks in the FPGA implement asynchronous clock domain crossing (both at the ADC and the DAC side). In addition, there is a possibility of bit-slips between data lanes of the ADC and the outputs of the receiving SERDES blocks in the FPGA. These are compensated for with an additional layer of buffering inside the FPGA. The total sum of all of these domain crossing and data-ordering-related delays result in an end-to-end latency of 285 ns. Of this, the DAC12DL3200 contributes approximately 6 ns of latency (see the data sheet spec), while the ADC12DL3200 adds a latency of approximately 8 ns. The remaining delay is from the FPGA logic used.

Figure 1-2 Low Latency LVDS-Based ADC Receiver and DAC Transmitter

Approach 2: To minimize the delay through the FPGA and obtain a true representation of the latency of the data converters, a simplified setup is created, where the FPGA is used as a combinatorial pass-through device. The FPGA logic passes just the MSB output of the ADC (through the FPGA) to the MSB input of the DAC. The FPGA does not carry out any re-timing of the signals to avoid any non-deterministic delays on account of clock domain crossing. Using this setup, the measured combined latency of ADC12DL3200 + FPGA + DAC12DL3200 + Device EVM routing is 32.8 ns .

Figure 1-3 Low Latency ADC EVM, Capture Card and Pattern Generator, and DAC EVM