SLASEA3D December 2016 – December 2023 DAC38RF80 , DAC38RF83 , DAC38RF84 , DAC38RF85 , DAC38RF90 , DAC38RF93
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The DAC38RFxx supports a number of basic pattern generation and verification of SerDes through the serial interface. Three pseudo random bit stream (PRBS) sequences are available, along with an alternating 0/1 pattern and a 20-bit user-defined sequence. The 27 - 1, 231 - 1 or 223 – 1 sequences implemented can often be found programmed into standard test equipment, such as a Bit Error Rate Tester (BERT). Pattern generation and verification selection is through field TESTPATT in register SRDS_CFG1 (8.5.86), as shown in Table 7-23.
TESTPATT | EFFECT |
---|---|
000 | Test mode disabled. |
001 | Alternating 0/1 Pattern. An alternating 0/1 pattern with a period of 2 UI. |
010 | Verify 27 - 1 PRBS. Uses a 7-bit LFSR with feedback polynomial x7 + x6 + 1. |
011 | Verify 223 - 1 PRBS. Uses an ITU O.150 conformant 23-bit LFSR with feedback polynomial x23 + x18 + 1. |
100 | Verify 231 - 1 PRBS. Uses an ITU O.150 conformant 31-bit LFSR with feedback polynomial x31 + x28 + 1. |
101 | User-defined 20-bit pattern. Uses the USR PATT IEEE1500 Tuning instruction field to specify the pattern. The default value is 0x66666. |
11x | Reserved. |
Pattern verification compares the output of the serial to parallel converter with an expected pattern. When there is a mismatch, the TESTFAIL bit is driven high, which can be programmed to come out the ALARM terminal by setting field DTEST in register DTEST (8.5.76) to “0011”.