SLASFB3 November   2023 DAC530A2W , DAC532A3W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Voltage Output
    6. 5.6  Electrical Characteristics: Current Output
    7. 5.7  Electrical Characteristics: Comparator Mode
    8. 5.8  Electrical Characteristics: General
    9. 5.9  Timing Requirements: I2C Standard Mode
    10. 5.10 Timing Requirements: I2C Fast Mode
    11. 5.11 Timing Requirements: I2C Fast-Mode Plus
    12. 5.12 Timing Requirements: SPI Write Operation
    13. 5.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    14. 5.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    15. 5.15 Timing Requirements: GPIO
    16. 5.16 Timing Diagrams
    17. 5.17 Typical Characteristics: Voltage Output
    18. 5.18 Typical Characteristics: Current Output
    19. 5.19 Typical Characteristics: Comparator
    20. 5.20 Typical Characteristics: General
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 6.3.2 Digital Input/Output
      3. 6.3.3 Nonvolatile Memory (NVM)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Voltage-Output Mode
        1. 6.4.1.1 Voltage Reference and DAC Transfer Function
          1. 6.4.1.1.1 Internal Reference
          2. 6.4.1.1.2 Power-Supply as Reference
      2. 6.4.2 Current-Output Mode
      3. 6.4.3 Comparator Mode
        1. 6.4.3.1 Programmable Hysteresis Comparator
        2. 6.4.3.2 Programmable Window Comparator
      4. 6.4.4 Fault-Dump Mode
      5. 6.4.5 Application-Specific Modes
        1. 6.4.5.1 Voltage Margining and Scaling
          1. 6.4.5.1.1 High-Impedance Output and PROTECT Input
          2. 6.4.5.1.2 Programmable Slew-Rate Control
        2. 6.4.5.2 Function Generation
          1. 6.4.5.2.1 Triangular Waveform Generation
          2. 6.4.5.2.2 Sawtooth Waveform Generation
          3. 6.4.5.2.3 Sine Waveform Generation
      6. 6.4.6 Device Reset and Fault Management
        1. 6.4.6.1 Power-On Reset (POR)
        2. 6.4.6.2 External Reset
        3. 6.4.6.3 Register-Map Lock
        4. 6.4.6.4 NVM Cyclic Redundancy Check (CRC)
          1. 6.4.6.4.1 NVM-CRC-FAIL-USER Bit
          2. 6.4.6.4.2 NVM-CRC-FAIL-INT Bit
      7. 6.4.7 General-Purpose Input/Output (GPIO) Modes
    5. 6.5 Programming
      1. 6.5.1 SPI Programming Mode
      2. 6.5.2 I2C Programming Mode
        1. 6.5.2.1 F/S Mode Protocol
        2. 6.5.2.2 I2C Update Sequence
          1. 6.5.2.2.1 Address Byte
          2. 6.5.2.2.2 Command Byte
        3. 6.5.2.3 I2C Read Sequence
  8. 7 Register Map
    1. 7.1  NOP Register (address = 00h) [reset = 0000h]
    2. 7.2  DAC-0-MARGIN-HIGH Register (address = 0Dh) [reset = 0000h]
    3. 7.3  DAC-1-MARGIN-HIGH Register (address = 13h) [reset = 0000h]
    4. 7.4  DAC-2-MARGIN-HIGH Register (address = 01h) [reset = 0000h]
    5. 7.5  DAC-0-MARGIN-LOW Register (address = 0Eh) [reset = 0000h]
    6. 7.6  DAC-1-MARGIN-LOW Register (address = 14h) [reset = 0000h]
    7. 7.7  DAC-2-MARGIN-LOW Register (address = 02h) [reset = 0000h]
    8. 7.8  DAC-0-GAIN-CONFIG Register (address = 0Fh) [reset = 0000h]
    9. 7.9  DAC-1-GAIN-CMP-CONFIG Register (address = 15h) [reset = 0000h]
    10. 7.10 DAC-2-GAIN-CONFIG Register (address = 03h) [reset = 0000h]
    11. 7.11 DAC-1-CMP-MODE-CONFIG Register (address = 17h) [reset = 0000h]
    12. 7.12 DAC-0-FUNC-CONFIG Register (address = 12h) [reset = 0000h]
    13. 7.13 DAC-1-FUNC-CONFIG Register (address = 18h) [reset = 0000h]
    14. 7.14 DAC-2-FUNC-CONFIG Register (address = 06h) [reset = 0000h]
    15. 7.15 DAC-0-DATA Register (address = 1Bh) [reset = 0000h]
    16. 7.16 DAC-1-DATA Register (address = 1Ch) [reset = 0000h]
    17. 7.17 DAC-2-DATA Register (address = 19h) [reset = 0000h]
    18. 7.18 COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
    19. 7.19 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
    20. 7.20 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
    21. 7.21 GENERAL-STATUS Register (address = 22h) [reset = 20h, DEVICE-ID, VERSION-ID]
    22. 7.22 CMP-STATUS Register (address = 23h) [reset = 000Ch]
    23. 7.23 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
    24. 7.24 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
    25. 7.25 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
    26. 7.26 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
    27. 7.27 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
    28. 7.28 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YBH|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.17 Typical Characteristics: Voltage Output

at TA = 25°C, VDD = 5.5 V, VDD as reference, gain = 1 ×, 10-bit resolution, and DAC outputs unloaded (unless otherwise noted)

GUID-20231112-SS0I-WX8G-5PTS-FDXRRWP0MW0V-low.svg
Internal reference, gain = 4 ×
Figure 5-4 Voltage Output INL vs Digital Input Code
GUID-20231112-SS0I-MB3B-3MFJ-P7RXF6G00B0W-low.svg
 
Figure 5-6 Voltage Output INL vs Temperature
GUID-20231112-SS0I-QP7M-HJKH-B2LMW38X0MWS-low.svg
Internal reference, gain = 4 ×
Figure 5-8 Voltage Output DNL vs Digital Input Code
GUID-20231112-SS0I-JMKN-RCLG-LSX3JRTBQHLR-low.svg
 
Figure 5-10 Voltage Output DNL vs Temperature
GUID-20231112-SS0I-VQLD-4S5D-VPTXJX43VK2G-low.svg
Internal reference, gain = 4 ×
Figure 5-12 Voltage Output TUE vs Digital Input Code
GUID-20231112-SS0I-QRPC-WXJ4-HTG8P9GFJQBN-low.svg
DAC channels at midscale
Figure 5-14 Voltage Output TUE vs Temperature
GUID-20231112-SS0I-5NKZ-5QX0-PPRK4ZBRHSMW-low.svg
 
Figure 5-16 Voltage Output Offset Error vs Temperature
GUID-20231112-SS0I-BNW5-KSFQ-TP7C9SGMQVGM-low.svg
 
Figure 5-18 Voltage Output AC PSRR vs Frequency
GUID-20231112-SS0I-NWVX-X9KD-7L17ZS0WW1PF-low.svg
 
Figure 5-20 Voltage Output Code-to-Code Glitch - Falling Edge
GUID-20231112-SS0I-15RD-MCQT-QQZX3LZ3W4WT-low.svg
Full scale to zero scale swing
Figure 5-22 Voltage Output Setting Time - Falling Edge
GUID-20231112-SS0I-P2MX-PFDC-WNGWZPBTMDJ0-low.svg
DAC at zero scale 
Figure 5-24 Voltage Output Power-Off Glitch
GUID-20231112-SS0I-PSWB-2NF0-BK0M2XWK44VB-low.svg
 
Figure 5-26 Voltage Output Noise Density
GUID-20231112-SS0I-NX5T-BGQF-HHN4L6MC3GSS-low.svg
f = 0.1 Hz to 10 Hz 
Figure 5-28 Voltage Output Flicker Noise
GUID-20231112-SS0I-NN4X-1CNS-PQVDQN4C3VBC-low.svg
 
Figure 5-5 Voltage Output INL vs Digital Input Code
GUID-20231112-SS0I-HTMN-9WCC-CKJLJK5WJNVV-low.svg
 
Figure 5-7 Voltage Output INL vs Supply Voltage
GUID-20231112-SS0I-WPXF-M5CN-3S976SSQFB4H-low.svg
 
Figure 5-9 Voltage Output DNL vs Digital Input Code
GUID-20231112-SS0I-JPN8-2W22-JBCCHKS9MFLQ-low.svg
 
Figure 5-11 Voltage Output DNL vs Supply Voltage
GUID-20231112-SS0I-TMLX-28HZ-LLJJLBKRDWNM-low.svg
 
Figure 5-13 Voltage Output TUE vs Digital Input Code
GUID-20231112-SS0I-HTTX-NN4Q-B2R74G4PHQBS-low.svg
DAC channels at midscale
Figure 5-15 Voltage Output TUE vs Supply Voltage
GUID-20231112-SS0I-PVBX-FRDX-TMLTMDWRCZWF-low.svg
 
Figure 5-17 Voltage Output Gain Error vs Temperature
GUID-20231112-SS0I-T14L-JJTR-CNHPR2HCPLX1-low.svg
 
Figure 5-19 Voltage Output Code-to-Code Glitch - Rising Edge
GUID-20231112-SS0I-VDDJ-2K6K-TWPJDDZHT1CH-low.svg
Zero scale to full scale swing 
Figure 5-21 Voltage Output Setting Time - Rising Edge
GUID-20231112-SS0I-FK7T-WCSX-6S7X1ZM5H9MC-low.svg
DAC in Hi-Z power-down mode
Figure 5-23 Voltage Output Power-On Glitch
GUID-20231112-SS0I-KWC7-FK6Q-PGXMZFLKJ8J2-low.svg
Internal reference, gain = 4 ×
Figure 5-25 Voltage Output Noise Density
GUID-20231112-SS0I-78T8-BMFQ-B27FC7PMPXCN-low.svg
Internal reference, gain = 4 ×, f = 0.1 Hz to 10 Hz
Figure 5-27 Voltage Output Flicker Noise