The DACx3204‑Q1 provides a feature to save a few registers into the NVM when the
FAULT-DUMP bit is triggered or the GPIO mapped to fault-dump (as shown in Table 7-18) is triggered. This feature is useful in system-level fault management to capture
the state of the device or system just before a fault is triggered, to allow
diagnosis after the fault has occurred. The registers saved when fault-dump is
triggered, are:
- CMP-STATUS[7:0]
- DAC-0-DATA[15:8]
- DAC-1-DATA[15:8]
- DAC-2-DATA[15:8]
- DAC-3-DATA[15:8]
Note: When the fault-dump cycle
is in progress, any change in the data can corrupt the final outcome. Make sure
the comparator and the DAC codes are stable during the NVM write
cycle.
Table 7-3 shows the storage format of the registers in the NVM.
Table 7-3 Fault-Dump NVM Storage
Format
| NVM
ROWS |
B31-B24 |
B23-B16 |
B15-B8 |
B7-B0 |
| Row1 |
CMP-STATUS[7:0] |
Don't care |
| Row2 |
DAC-0-DATA[15:8] |
DAC-1-DATA[15:8] |
DAC-2-DATA[15:8] |
DAC-3-DATA[15:8] |
The data captured in the NVM after the
fault dump can be read in a specific sequence:
- Set the EE-READ-ADDR bit to
0b in the COMMON-CONFIG register, to select row1 of the NVM.
- Trigger the read of the
selected NVM row by writing 1 to the READ-ONE-TRIG in the COMMON-TRIGGER
register; this bit autoresets. This action copies that data from the
selected NVM row to SRAM addresses 0x9D (LSB 16 bits from the NVM) and 0x9E
(MSB 16 bits from the NVM).
- To read the SRAM data:
- Write 0x009D to the
SRAM-CONFIG register.
- Read the data from
the SRAM-DATA register to get the LSB 16 bits.
- Write 0x009E to the
SRAM-CONFIG register.
- Read the data from
the SRAM-DATA register again to get the MSB bits.
- Set the EE-READ-ADDR bit to
1b in the COMMON-CONFIG register, to select row2 of the NVM. Repeat steps 2
and 3.