SLASE30 October   2020 DAC43401-Q1 , DAC53401-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2C Standard Mode
    7. 7.7  Timing Requirements: I2C Fast Mode
    8. 7.8  Timing Requirements: I2C Fast Mode Plus
    9. 7.9  Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
    10. 7.10 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 Reference Selection and DAC Transfer Function
          1. 8.3.1.1.1 Power Supply as Reference
          2. 8.3.1.1.2 Internal Reference
      2. 8.3.2 DAC Update
        1. 8.3.2.1 DAC Update Busy
      3. 8.3.3 Nonvolatile Memory (EEPROM or NVM)
        1. 8.3.3.1 NVM Cyclic Redundancy Check
        2. 8.3.3.2 NVM_CRC_ALARM_USER Bit
        3. 8.3.3.3 NVM_CRC_ALARM_INTERNAL Bit
      4. 8.3.4 Programmable Slew Rate
      5. 8.3.5 Power-on-Reset (POR)
      6. 8.3.6 Software Reset
      7. 8.3.7 Device Lock Feature
      8. 8.3.8 PMBus Compatibility
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Down Mode
      2. 8.4.2 Continuous Waveform Generation (CWG) Mode
      3. 8.4.3 PMBus Compatibility Mode
    5. 8.5 Programming
      1. 8.5.1 F/S Mode Protocol
      2. 8.5.2 I2C Update Sequence
        1. 8.5.2.1 Address Byte
        2. 8.5.2.2 Command Byte
      3. 8.5.3 I2C Read Sequence
    6. 8.6 Register Map
      1. 8.6.1 STATUS Register (address = D0h) [reset = 000Ch or 0014h]
      2. 8.6.2 GENERAL_CONFIG Register (address = D1h) [reset = 01F0h]
      3. 8.6.3 TRIGGER Register (address = D3h) [reset = 0008h]
      4. 8.6.4 DAC_DATA Register (address = 21h) [reset = 0000h]
      5. 8.6.5 DAC_MARGIN_HIGH Register (address = 25h) [reset = 0000h]
      6. 8.6.6 DAC_MARGIN_LOW Register (address = 26h) [reset = 0000h]
      7. 8.6.7 PMBUS_OPERATION Register (address = 01h) [reset = 0000h]
      8. 8.6.8 PMBUS_STATUS_BYTE Register (address = 78h) [reset = 0000h]
      9. 8.6.9 PMBUS_VERSION Register (address = 98h) [reset = 2200h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Programmable LED Biasing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Power-Supply Margining
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.4 Programmable Slew Rate

When the DAC data registers are written, the voltage on DAC output (VOUT) immediately transitions to the new code following the slew rate and settling time specified in Section 7.5. The slew rate control feature allows the user to control the rate at which the output voltage (VOUT) changes. When this feature is enabled (using SLEW_RATE[3:0] bits), the DAC output changes from the current code to the code in MARGIN_HIGH (address 25h) or MARGIN_LOW (address 26h) registers (when margin high or low commands are issued to the DAC) using the step and rate set in CODE_STEP and SLEW_RATE bits. With the default slew rate control setting (CODE_STEP and SLEW_RATE bits, address D1h), the output changes smoothly at a rate limited by the output drive circuitry and the attached load. Using this feature, the output steps digitally at a rate defined by bits CODE_STEP and SLEW_RATE on address D1h. SLEW_RATE defines the rate at which the digital slew updates; CODE_STEP defines the amount by which the output value changes at each update. Table 8-2 and Table 8-3 show different settings for CODE_STEP and SLEW_RATE.

When the slew rate control feature is used, the output changes happen at the programmed slew rate. This configuration results in a staircase formation at the output. Do not write to CODE_STEP, SLEW_RATE, or DAC_DATA during the output slew.

Table 8-2 Code Step
REGISTER ADDRESS AND NAMECODE_STEP[2]CODE_STEP[1]CODE_STEP[0]COMMENT
D1h, GENERAL_CONFIG000Code step size = 1 LSB (default)
001Code step size = 2 LSB
010Code step size = 3 LSB
011Code step size = 4 LSB
100Code step size = 6 LSB
101Code step size = 8 LSB
110Code step size = 16 LSB
111Code step size = 32 LSB
Table 8-3 Slew Rate
REGISTER ADDRESS AND NAME SLEW_RATE[3] SLEW_RATE[2] SLEW_RATE[1] SLEW_RATE[0] COMMENT
D1h, GENERAL_CONFIG 0 0 0 0 25.6 µs
(per step)
0 0 0 1 25.6 µs × 1.25
(per step)
0 0 1 0 25.6 µs × 1.50
(per step)
0 0 1 1 25.6 µs × 1.75
(per step)
0 1 0 0 204.8 µs
(per step)
0 1 0 1 204.8 µs × 1.25
(per step)
0 1 1 0 204.8 µs × 1.50
(per step)
0 1 1 1 204.8 µs × 1.75
(per step)
1 0 0 0 1.6384 ms (per step)
1 0 0 1 1.6384 ms × 1.25
(per step)
1 0 1 0 1.6384 ms × 1.50
(per step)
1 0 1 1 1.6384 ms × 1.75
(per step)
1 1 0 0 12 µs (per step)
1 1 0 1 8 µs (per step)
1 1 1 0 4 µs (per step)
1 1 1 1 No slew (default)