at TA = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)
Figure 7-22 Integral Linearity Error vs Supply Voltage
Figure 7-24 Total
Unadjusted Error vs Supply Voltage
Figure 7-26 Offset Error vs Supply Voltage
Figure 7-28 Full-Scale Error vs Supply Voltage
Figure 7-30 Supply Current vs Digital Input Code![Supply Current vs Temperature GUID-20201201-CA0I-MGZ2-W5P6-7MBKG70GF1ZT-low.svg](/ods/images/SLASEY5/GUID-20201201-CA0I-MGZ2-W5P6-7MBKG70GF1ZT-low.svg)
Internal reference (gain = 4x), DAC at midscale |
Figure 7-32 Supply Current vs Temperature![Power-Down Current vs Temperature GUID-75CBB65C-CF33-4344-9D16-B5CE7F33A751-low.gif](/ods/images/SLASEY5/GUID-75CBB65C-CF33-4344-9D16-B5CE7F33A751-low.gif)
Reference = VDD, DAC powered down |
Figure 7-34 Power-Down Current vs Temperature![Glitch Impulse, Rising Edge, 1-LSB Step GUID-20201130-CA0I-PJDQ-FR5S-8CKV9XRG2HZJ-low.svg](/ods/images/SLASEY5/GUID-20201130-CA0I-PJDQ-FR5S-8CKV9XRG2HZJ-low.svg)
Reference = VDD = 5.5 V, DAC code transition
from midscale to midscale + 1 LSB, DAC load = 5kΩ ||
200pF |
Figure 7-36 Glitch Impulse, Rising Edge, 1-LSB Step![Full-Scale Settling Time, Rising Edge GUID-20201204-CA0I-W6QW-FF34-SFJ41X3WWSFZ-low.svg](/ods/images/SLASEY5/GUID-20201204-CA0I-W6QW-FF34-SFJ41X3WWSFZ-low.svg)
Reference = VDD = 5.5 V, DAC load = 5kΩ ||
200pF |
Figure 7-38 Full-Scale Settling Time, Rising Edge
Figure 7-40 Power-on Glitch![Clock
Feedthrough GUID-20201130-CA0I-0VFX-NJRG-12RWRB7F2BXX-low.svg](/ods/images/SLASEY5/GUID-20201130-CA0I-0VFX-NJRG-12RWRB7F2BXX-low.svg)
Reference = VDD = 5.5 V, Fast+ mode, DAC at
midscale, DAC load = 5kΩ || 200pF |
Figure 7-42 Clock
Feedthrough
Figure 7-44 DAC
Output Noise Spectral Density![DAC
Output Noise: 0.1 Hz to 10 Hz GUID-20201204-CA0I-WQST-PRXZ-HWNNBQW5JSHV-low.svg](/ods/images/SLASEY5/GUID-20201204-CA0I-WQST-PRXZ-HWNNBQW5JSHV-low.svg)
Reference = VDD = 5.5 V, DAC at
midscale |
Figure 7-46 DAC
Output Noise: 0.1 Hz to 10 Hz
Figure 7-23 Differential Linearity Error vs Supply Voltage
Figure 7-25 Zero-Code Error vs Supply Voltage
Figure 7-27 Gain
Error vs Supply Voltage
Figure 7-29 Supply Current vs Digital Input Code![Supply Current vs Temperature GUID-20201201-CA0I-V6QZ-PBKX-ZPDJJK87N3BQ-low.svg](/ods/images/SLASEY5/GUID-20201201-CA0I-V6QZ-PBKX-ZPDJJK87N3BQ-low.svg)
Reference = VDD, DAC at midscale |
Figure 7-31 Supply Current vs Temperature
Figure 7-33 Supply Current vs Supply Voltage
Figure 7-35 Source and Sink Capability![Glitch Impulse, Falling Edge, 1-LSB Step GUID-20201130-CA0I-KQFD-1BNC-VDXZD9G7VP1R-low.svg](/ods/images/SLASEY5/GUID-20201130-CA0I-KQFD-1BNC-VDXZD9G7VP1R-low.svg)
Reference = VDD = 5.5 V, DAC code transition
from midscale to midscale – 1 LSB, DAC load = 5kΩ ||
200pF |
Figure 7-37 Glitch Impulse, Falling Edge, 1-LSB Step![Full-Scale Settling Time, Falling Edge GUID-20201204-CA0I-WD2Q-1VGJ-3HJ2VVLPXLDZ-low.svg](/ods/images/SLASEY5/GUID-20201204-CA0I-WD2Q-1VGJ-3HJ2VVLPXLDZ-low.svg)
Reference = VDD = 5.5 V, DAC load = 5kΩ ||
200pF |
Figure 7-39 Full-Scale Settling Time, Falling Edge
Figure 7-41 Power-off Glitch![DAC Output AC PSRR vs Frequency GUID-A0B349D9-A4FD-4558-8D16-08EF35592A7D-low.gif](/ods/images/SLASEY5/GUID-A0B349D9-A4FD-4558-8D16-08EF35592A7D-low.gif)
Internal reference (gain = 4x), VDD = 5.25 V + 0.25 VPP, DAC at midscale, DAC load = 5kΩ || 200pF |
Figure 7-43 DAC Output AC PSRR vs Frequency![DAC
Output Noise Spectral Density GUID-20201201-CA0I-CXSP-N91W-1XCL41M3TKW8-low.svg](/ods/images/SLASEY5/GUID-20201201-CA0I-CXSP-N91W-1XCL41M3TKW8-low.svg)
Internal reference (gain = 4x), VDD = 5.5
V |
Figure 7-45 DAC
Output Noise Spectral Density![DAC
Output Noise: 0.1 Hz to 10 Hz GUID-20201204-CA0I-LHRM-MQSP-M4QFGDXVZGQL-low.svg](/ods/images/SLASEY5/GUID-20201204-CA0I-LHRM-MQSP-M4QFGDXVZGQL-low.svg)
Internal reference (gain = 4x), VDD = 5.5 V,
DAC at midscale |
Figure 7-47 DAC
Output Noise: 0.1 Hz to 10 Hz