SLASEY5 December   2020 DAC43701 , DAC53701

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2C Standard Mode
    7. 7.7  Timing Requirements: I2C Fast Mode
    8. 7.8  Timing Requirements: I2C Fast Mode Plus
    9. 7.9  Timing Requirements: GPI
    10. 7.10 Timing Diagram
    11. 7.11 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
    12. 7.12 Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
    13. 7.13 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 Reference Selection and DAC Transfer Function
          1. 8.3.1.1.1 Power Supply as Reference
          2. 8.3.1.1.2 Internal Reference
      2. 8.3.2 General-Purpose Input (GPI)
      3. 8.3.3 DAC Update
        1. 8.3.3.1 DAC Update Busy
      4. 8.3.4 Nonvolatile Memory (EEPROM or NVM)
        1. 8.3.4.1 NVM Cyclic Redundancy Check
        2. 8.3.4.2 NVM_CRC_ALARM_USER Bit
        3. 8.3.4.3 NVM_CRC_ALARM_INTERNAL Bit
      5. 8.3.5 Programmable Slew Rate
      6. 8.3.6 Power-on-Reset (POR)
      7. 8.3.7 Software Reset
      8. 8.3.8 Device Lock Feature
      9. 8.3.9 PMBus Compatibility
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Down Mode
      2. 8.4.2 Continuous Waveform Generation (CWG) Mode
      3. 8.4.3 PMBus Compatibility Mode
      4. 8.4.4 Medical Alarm Generation Mode
        1. 8.4.4.1 Low-Priority Alarm
        2. 8.4.4.2 Medium-Priority Alarm
        3. 8.4.4.3 High-Priority Alarm
        4. 8.4.4.4 Interburst Time
        5. 8.4.4.5 Pulse Off Time
        6. 8.4.4.6 Pulse On Time
    5. 8.5 Programming
      1. 8.5.1 F/S Mode Protocol
      2. 8.5.2 I2C Update Sequence
        1. 8.5.2.1 Address Byte
          1. 8.5.2.1.1 Slave Address Configuration
        2. 8.5.2.2 Command Byte
      3. 8.5.3 I2C Read Sequence
    6. 8.6 Register Map
      1. 8.6.1  STATUS Register (address = D0h) [reset = 000Ch or 0014h]
      2. 8.6.2  GENERAL_CONFIG Register (address = D1h) [reset = 01F0h]
      3. 8.6.3  CONFIG2 Register (address = D2h) [reset = 0000h]
      4. 8.6.4  TRIGGER Register (address = D3h) [reset = 0008h]
      5. 8.6.5  DAC_DATA Register (address = 21h) [reset = 0000h]
      6. 8.6.6  DAC_MARGIN_HIGH Register (address = 25h) [reset = 0000h]
      7. 8.6.7  DAC_MARGIN_LOW Register (address = 26h) [reset = 0000h]
      8. 8.6.8  PMBUS_OPERATION Register (address = 01h) [reset = 0000h]
      9. 8.6.9  PMBUS_STATUS_BYTE Register (address = 78h) [reset = 0000h]
      10. 8.6.10 PMBUS_VERSION Register (address = 98h) [reset = 2200h]
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Appliance Light Fade-In Fade-Out
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Power-Supply Margining
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Medical Alarm Generation
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Typical Characteristics

at TA = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)

GUID-50469457-C6AA-4A51-BE5D-74B7DB2ABE3A-low.gif
Reference = VDD
Figure 7-22 Integral Linearity Error vs Supply Voltage
GUID-56B7DC6E-9F26-4F6A-A569-EB06A7790C55-low.gif
Reference = VDD
Figure 7-24 Total Unadjusted Error vs Supply Voltage
GUID-02259237-CCA7-4D41-8163-806D771C145B-low.gif
Reference = VDD
Figure 7-26 Offset Error vs Supply Voltage
GUID-CFAEC155-B774-4F4E-8F1E-601F1A35B53C-low.gif
Reference = VDD
Figure 7-28 Full-Scale Error vs Supply Voltage
GUID-20201201-CA0I-XBKX-SCCR-PCM4M3DKTF6G-low.svg
VDD = 5.5 V
Figure 7-30 Supply Current vs Digital Input Code
GUID-20201201-CA0I-MGZ2-W5P6-7MBKG70GF1ZT-low.svg
Internal reference (gain = 4x), DAC at midscale
Figure 7-32 Supply Current vs Temperature
GUID-75CBB65C-CF33-4344-9D16-B5CE7F33A751-low.gif
Reference = VDD, DAC powered down
Figure 7-34 Power-Down Current vs Temperature
GUID-20201130-CA0I-PJDQ-FR5S-8CKV9XRG2HZJ-low.svg
Reference = VDD = 5.5 V, DAC code transition from midscale to midscale + 1 LSB, DAC load = 5kΩ || 200pF
Figure 7-36 Glitch Impulse, Rising Edge, 1-LSB Step
GUID-20201204-CA0I-W6QW-FF34-SFJ41X3WWSFZ-low.svg
Reference = VDD = 5.5 V, DAC load = 5kΩ || 200pF
Figure 7-38 Full-Scale Settling Time, Rising Edge
GUID-26001884-0298-4D20-A642-29A373C25239-low.gif
Reference = VDD = 5.5 V
Figure 7-40 Power-on Glitch
GUID-20201130-CA0I-0VFX-NJRG-12RWRB7F2BXX-low.svg
Reference = VDD = 5.5 V, Fast+ mode, DAC at midscale, DAC load = 5kΩ || 200pF
Figure 7-42 Clock Feedthrough
GUID-20201201-CA0I-75WV-4WSX-PN6M8JBVPHX1-low.svg
Reference = VDD = 5.5 V
Figure 7-44 DAC Output Noise Spectral Density
GUID-20201204-CA0I-WQST-PRXZ-HWNNBQW5JSHV-low.svg
Reference = VDD = 5.5 V, DAC at midscale
Figure 7-46 DAC Output Noise: 0.1 Hz to 10 Hz
GUID-68BE43B2-3161-40C4-A197-D988B964F507-low.gif
Reference = VDD
Figure 7-23 Differential Linearity Error vs Supply Voltage
GUID-DB4C4995-84EB-4AD5-9B6D-1D061BC78553-low.gif
Reference = VDD
Figure 7-25 Zero-Code Error vs Supply Voltage
GUID-6FEF8A57-80C9-4990-85E7-ADD02D2E24AD-low.gif
Reference = VDD
Figure 7-27 Gain Error vs Supply Voltage
GUID-20201201-CA0I-TKHT-RNVC-16NNVVSHZXM5-low.svg
VDD = 1.8 V
Figure 7-29 Supply Current vs Digital Input Code
GUID-20201201-CA0I-V6QZ-PBKX-ZPDJJK87N3BQ-low.svg
Reference = VDD, DAC at midscale
Figure 7-31 Supply Current vs Temperature
GUID-5E0877FC-2F31-4866-9570-C9422AA631B1-low.gif
DAC at midscale
Figure 7-33 Supply Current vs Supply Voltage
GUID-7F146A73-1BDB-4844-847D-2B716E23CCF0-low.gif
 
Figure 7-35 Source and Sink Capability
GUID-20201130-CA0I-KQFD-1BNC-VDXZD9G7VP1R-low.svg
Reference = VDD = 5.5 V, DAC code transition from midscale to midscale – 1 LSB, DAC load = 5kΩ || 200pF
Figure 7-37 Glitch Impulse, Falling Edge, 1-LSB Step
GUID-20201204-CA0I-WD2Q-1VGJ-3HJ2VVLPXLDZ-low.svg
Reference = VDD = 5.5 V, DAC load = 5kΩ || 200pF
Figure 7-39 Full-Scale Settling Time, Falling Edge
GUID-788A235E-DBEB-4DF6-AC10-7D0A609D3F4B-low.gif
Reference = VDD = 5.5 V
Figure 7-41 Power-off Glitch
GUID-A0B349D9-A4FD-4558-8D16-08EF35592A7D-low.gif
Internal reference (gain = 4x), VDD = 5.25 V + 0.25 VPP, DAC at midscale, DAC load = 5kΩ || 200pF
Figure 7-43 DAC Output AC PSRR vs Frequency
GUID-20201201-CA0I-CXSP-N91W-1XCL41M3TKW8-low.svg
Internal reference (gain = 4x), VDD = 5.5 V
Figure 7-45 DAC Output Noise Spectral Density
GUID-20201204-CA0I-LHRM-MQSP-M4QFGDXVZGQL-low.svg
Internal reference (gain = 4x), VDD = 5.5 V, DAC at midscale
Figure 7-47 DAC Output Noise: 0.1 Hz to 10 Hz