SLASF63 june   2023 DAC539E4W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Threshold DAC
    6. 6.6  Electrical Characteristics: Comparator
    7. 6.7  Electrical Characteristics: General
    8. 6.8  Timing Requirements: I2C Standard Mode
    9. 6.9  Timing Requirements: I2C Fast Mode
    10. 6.10 Timing Requirements: I2C Fast Mode Plus
    11. 6.11 Timing Requirements: SPI Write Operation
    12. 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    14. 6.14 Timing Diagrams
    15. 6.15 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 7.3.2 Threshold DAC
        1. 7.3.2.1 Voltage Reference and DAC Transfer Function
          1. 7.3.2.1.1 Power-Supply as Reference
          2. 7.3.2.1.2 Internal Reference
          3. 7.3.2.1.3 External Reference
      3. 7.3.3 Look-Up Table (LUT)
      4. 7.3.4 Programming Interface
      5. 7.3.5 Nonvolatile Memory (NVM)
        1. 7.3.5.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.5.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.5.1.2 NVM-CRC-FAIL-INT Bit
      6. 7.3.6 Power-On Reset (POR)
      7. 7.3.7 External Reset
      8. 7.3.8 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Comparator Mode
        1. 7.4.1.1 Programmable Hysteresis Comparator
      2. 7.4.2 Power-Down Mode
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-x-MARGIN-HIGH Register (address = 01h, 07h, 0Dh, 13h) [reset = 0000h]
      3. 7.6.3  DAC-x-MARGIN-LOW Register (address = 02h, 08h, 0Eh, 14h) [reset = 0000h]
      4. 7.6.4  DAC-x-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h) [reset = 0401h]
      5. 7.6.5  DAC-x-CMP-MODE-CONFIG Register (address = 05h, 0Bh, 11h, 17h) [reset = 0000h]
      6. 7.6.6  COMMON-CONFIG Register (address = 1Fh) [reset = 1249h]
      7. 7.6.7  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      8. 7.6.8  COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
      9. 7.6.9  GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      10. 7.6.10 CMP-STATUS Register (address = 23h) [reset = 0000h]
      11. 7.6.11 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 8040h]
      12. 7.6.12 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      13. 7.6.13 STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      14. 7.6.14 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      15. 7.6.15 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      16. 7.6.16 DAC-x-DATA Register (SRAM address = 21h, 22h, 23h, 24h) [reset = 8000h]
      17. 7.6.17 LUT-x-DATA Register (SRAM address = 25h through 34h) [reset = (see register description)]
      18. 7.6.18 LOOP-WAIT Register (SRAM address = 35h) [reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YBH|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-20230604-CA0I-NHDH-XQ9X-GQFXVTQHQ8VZ-low.svg Figure 5-1 YBH Package, 16-pin DSBGA (Top View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NO. NAME
A1 MODE Power External reference (VREF) or MODE input. Connect a capacitor (approximately 0.1 μF) between MODE and AGND.
Use a pullup resistor to VDD when the external reference is not used. Do not ramp up this pin before VDD. In case an external reference is used, make sure the reference ramps up after VDD.
For programming mode, pull this pin low. For standalone mode, pull this pin high or connect to external reference.
A2 OUT3 Output Comparator output 3. For easy PCB routing, make this pin Hi-Z using register settings and short AIN3 and OUT3.
A3 OUT2 Output Comparator output 2. For easy PCB routing, make this pin Hi-Z using register settings and short AIN2 and OUT2.
A4 GPO3 Output Programming mode: This pin is configurable as SDO. For SDO function, connect the pin to the I/O voltage with an external pullup resistor. If unused, connect this pin to VDD or AGND using an external resistor. This pin can ramp up before VDD.
Standalone mode: General-purpose output 3. Connect this pin to the I/O voltage using an external pullup resistor.
B1 VDD Power Supply voltage.
B2 AIN3 Input Analog input pin for channel 3.
B3 AIN2 Input Analog input pin for channel 2.
B4 GPO2 Input/Output Programming mode (SCL/SYNC): I2C serial interface clock or SPI chip select input. Connect this to the I/O voltage using an external pullup resistor. This pin can ramp up before VDD.
Standalone mode: General-purpose output 2. Connect this pin to the I/O voltage using an external pullup resistor.
C1 AGND Ground Ground reference point for all circuitry on the device.
C2 AIN0 Input Analog input pin for channel 0.
C3 AIN1 Input Analog input pin for channel 1.
C4 GPO1 Input/Output Programming mode (A0/SDI): Address configuration pin for I2C or serial data input for SPI.
For A0, connect this pin to VDD, AGND, SDA, or SCL for address configuration.
For SDI, this pin need not be pulled up or pulled down. This pin can ramp up before VDD.
Standalone mode: General-purpose output 1. Connect this pin to the I/O voltage using an external pullup resistor.
D1 CAP Power External bypass capacitor for the internal LDO. Connect a capacitor (approximately 1.5 μF) between CAP and AGND.
D2 OUT0 Output Comparator output 0. For easy PCB routing, make this pin Hi-Z using register settings and short AIN0 and OUT0.
D3 OUT1 Output Comparator output 1. For easy PCB routing, make this pin Hi-Z using register settings and short AIN1 and OUT1.
D4 GPO0 Input/Output Programming mode (SDA/SCLK): Bidirectional I2C serial data bus or SPI clock input. Connect this pin to the I/O voltage using an external pullup resistor in I2C mode. This pin can ramp up before VDD.
Standalone mode: General-purpose output 0. Connect this pin to the I/O voltage using an external pullup resistor.