SLASF63A June   2023  – July 2025 DAC539E4W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Threshold DAC
    6. 5.6  Electrical Characteristics: Comparator
    7. 5.7  Electrical Characteristics: General
    8. 5.8  Timing Requirements: I2C Standard Mode
    9. 5.9  Timing Requirements: I2C Fast Mode
    10. 5.10 Timing Requirements: I2C Fast Mode Plus
    11. 5.11 Timing Requirements: SPI Write Operation
    12. 5.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    13. 5.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    14. 5.14 Timing Diagrams
    15. 5.15 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 6.3.2 Threshold DAC
        1. 6.3.2.1 Voltage Reference and DAC Transfer Function
          1. 6.3.2.1.1 Power-Supply as Reference
          2. 6.3.2.1.2 Internal Reference
          3. 6.3.2.1.3 External Reference
      3. 6.3.3 Look-Up Table (LUT)
      4. 6.3.4 Programming Interface
      5. 6.3.5 Nonvolatile Memory (NVM)
        1. 6.3.5.1 NVM Cyclic Redundancy Check (CRC)
          1. 6.3.5.1.1 NVM-CRC-FAIL-USER Bit
          2. 6.3.5.1.2 NVM-CRC-FAIL-INT Bit
      6. 6.3.6 Power-On Reset (POR)
      7. 6.3.7 External Reset
      8. 6.3.8 Register-Map Lock
    4. 6.4 Device Functional Modes
      1. 6.4.1 Comparator Mode
        1. 6.4.1.1 Programmable Hysteresis Comparator
      2. 6.4.2 Power-Down Mode
    5. 6.5 Programming
      1. 6.5.1 SPI Programming Mode
      2. 6.5.2 I2C Programming Mode
        1. 6.5.2.1 F/S Mode Protocol
        2. 6.5.2.2 I2C Update Sequence
          1. 6.5.2.2.1 Address Byte
          2. 6.5.2.2.2 Command Byte
        3. 6.5.2.3 I2C Read Sequence
    6. 6.6 Register Maps
      1. 6.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 6.6.2  DAC-x-MARGIN-HIGH Register (address = 01h, 07h, 0Dh, 13h) [reset = 0000h]
      3. 6.6.3  DAC-x-MARGIN-LOW Register (address = 02h, 08h, 0Eh, 14h) [reset = 0000h]
      4. 6.6.4  DAC-x-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h) [reset = 0401h]
      5. 6.6.5  DAC-x-CMP-MODE-CONFIG Register (address = 05h, 0Bh, 11h, 17h) [reset = 0000h]
      6. 6.6.6  COMMON-CONFIG Register (address = 1Fh) [reset = 1249h]
      7. 6.6.7  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      8. 6.6.8  COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
      9. 6.6.9  GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      10. 6.6.10 CMP-STATUS Register (address = 23h) [reset = 0000h]
      11. 6.6.11 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 8040h]
      12. 6.6.12 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      13. 6.6.13 STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      14. 6.6.14 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      15. 6.6.15 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      16. 6.6.16 DAC-x-DATA Register (SRAM address = 21h, 22h, 23h, 24h) [reset = 8000h]
      17. 6.6.17 LUT-x-DATA Register (SRAM address = 25h through 34h) [reset = (see register description)]
      18. 6.6.18 LOOP-WAIT Register (SRAM address = 35h) [reset = 0000h]
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YBH|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 

Copyright © 2024, Texas Instruments Incorporated