Refer to the PDF data sheet for device specific package drawings
The 12-bit DAC63004 and 10-bit DAC53004 (DACx3004) are a pin-compatible family of ultra-low-power, quad-channel, buffered, voltage-output and current-output smart digital-to-analog converters (DACs). These DACx3004 support Hi-Z power-down mode and Hi-Z output during power-off condition. The DAC outputs provide a force-sense option for use as a programmable comparator and current sink. The multifunction GPIO, function generation, and NVM enable these smart DACs for processor-less applications and design reuse. These devices automatically detect I2C, PMBus, and SPI interfaces and contain an internal reference.
The feature set combined with the tiny package and ultra-low power make these smart DACs an excellent choice for applications such as land mobile radios, pulseoximeters, notebook PCs, and other battery-operated applications for biasing, calibration, and waveform generation.
PART NUMBER | PACKAGE(1) | BODY SIZE (NOM) |
---|---|---|
DACx3004 | WQFN (16) | 3.00 mm x 3.00 mm |
Changes from Revision * (April 2021) to Revision A (December 2021)
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | FB3 | Input | Voltage feedback pin for channel 3. In voltage-output mode, connect to OUT3 for closed-loop amplifier output. In current-output mode, keep the FB3 pin unconnected to minimize leakage current. |
2 | OUT3 | Output | Analog output voltage from DAC channel 3. |
3 | OUT2 | Output | Analog output voltage from DAC channel 2. |
4 | FB2 | Input | Voltage feedback pin for channel 2. In voltage-output mode, connect to OUT2 for closed-loop amplifier output. In current-output mode, keep the FB2 pin unconnected to minimize leakage current. |
5 | GPIO/SDO | Input/Output | General-purpose input/output configurable as LDAC, PD, PROTECT, RESET, SDO, and STATUS. For STATUS and SDO, connect the pin to the IO voltage with an external pullup resistor. If unused, connect the GPIO pin to VDD or AGND using an external resistor. This pin can ramp up before VDD. |
6 | SCL/SYNC | Output | I2C serial interface clock or SPI chip select input. This pin must be connected to the IO voltage using an external pullup resistor. This pin can ramp up before VDD. |
7 | A0/SDI | Input | Address
configuration pin for I2C or serial data input for SPI.
For A0, connect this pin to VDD, AGND, SDA, or SCL for address configuration (Section 7.5.2.2.1). For SDI, this pin need not be pulled up or pulled down. This pin can ramp up before VDD. |
8 | SDA/SCLK | Input/Output | Bidirectional I2C serial data bus or SPI clock input. This pin must be connected to the IO voltage using an external pullup resistor in the I2C mode. This pin can ramp up before VDD. |
9 | FB1 | Input | Voltage feedback pin for channel 1. In voltage-output mode, connect to OUT1 for closed-loop amplifier output. In current-output mode, keep the FB1 pin unconnected to minimize leakage current. |
10 | OUT1 | Output | Analog output voltage from DAC channel 1. |
11 | OUT0 | Output | Analog output voltage from DAC channel 0. |
12 | FB0 | Input | Voltage feedback pin for channel 0. In voltage-output mode, connect to OUT0 for closed-loop amplifier output. In current-output mode, keep the FB0 pin unconnected to minimize leakage current. |
13 | CAP | Power | External bypass capacitor for the internal LDO. Connect a capacitor (approximately 1.5 μF) between CAP and AGND. |
14 | AGND | Ground | Ground reference point for all circuitry on the device. |
15 | VDD | Power | Supply voltage. |
16 | VREF | Power | External
reference input. Connect a capacitor (approximately 0.1 μF) between
VREF and AGND. Use a pullup resistor to VDD when the external reference is not used. This pin must not ramp up before VDD. In case an external reference is used, make sure the reference ramps up after VDD. |
— | Thermal Pad | Ground | Connect the thermal pad to AGND. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VDD | Supply voltage, VDD to AGND | –0.3 | 6 | V |
Digital inputs to AGND | –0.3 | VDD + 0.3 | V | |
CAP to AGND | –0.3 | 1.65 | V | |
VFBX to AGND | –0.3 | VDD + 0.3 | V | |
VOUTX to AGND | –0.3 | VDD + 0.3 | V | |
VREF | External reference, VREF to AGND | –0.3 | VDD + 0.3 | V |
Current into any pin except the OUTx pins | –10 | 10 | mA | |
TJ | Junction temperature | –40 | 150 | °C |
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VDD | Positive supply voltage to ground (AGND) | 1.7 | 5.5 | V | |
VREF | External reference to ground (AGND) | 1.7 | VDD | V | |
VIH | Digital input high voltage, 1.7 V < VDD ≤ 5.5 V | 1.62 | V | ||
VIL | Digital input low voltage | 0.4 | V | ||
CCAP | External capacitor on CAP pin | 0.5 | 15 | μF | |
TA | Ambient temperature | –40 | 125 | °C |
THERMAL METRIC(1) | DACx3004 |
UNIT | |
---|---|---|---|
RTE (WQFN) | |||
16 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 49 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 50 | °C/W |
RθJB | Junction-to-board thermal resistance | 24.1 | °C/W |
ΨJT | Junction-to-top characterization parameter | 1.1 | °C/W |
ΨJB | Junction-to-board characterization parameter | 24.1 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 8.7 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
STATIC PERFORMANCE | ||||||
Resolution | DAC63004 | 12 | Bits | |||
DAC53004 | 10 | |||||
INL | Integral nonlinearity(1) | DAC63004 | –4 | 4 | LSB | |
DAC53004 | –1 | 1 | ||||
DNL | Differential nonlinearity(1) | –1 | 1 | LSB | ||
Zero-code error(4) | Code 0d into DAC, external reference, VDD = 5.5 V | 6 | 12 | mV | ||
Code 0d into DAC, internal VREF, gain = 4x, VDD = 5.5 V | 6 | 15 | ||||
Zero-code error temperature coefficient(4) | Code 0d into DAC | ±10 | µV/°C | |||
Offset error(4) (6) | 1.7 V ≤ VDD < 2.7 V, FBx pin shorted to OUTx, DAC code: 32d for 12-bit resolution, 8d for 10-bit resolution |
–0.75 | 0.3 | 0.75 | %FSR | |
2.7 V ≤ VDD ≤ 5.5 V, FBx pin shorted to OUTx, DAC code: 32d for 12-bit resolution, 8d for 10-bit resolution |
–0.5 | 0.25 | 0.5 | |||
Offset-error temperature coefficient(4) | FBx pin shorted to OUTx, DAC code: 32d for 12-bit resolution, 8d for 10-bit resolution |
±0.0003 | %FSR/°C | |||
Gain error(4) | Between end-point codes: 32d to 4064d for 12-bit resolution, 8d to 1016d for 10-bit resolution | –0.5 | 0.25 | 0.5 | %FSR | |
Gain-error temperature coefficient(4) | Between end-point codes: 32d to 4064d for 12-bit resolution, 8d to 1016d for 10-bit resolution | ±0.0008 | %FSR/°C | |||
Full-scale error(4) (6) | 1.7 V ≤ VDD < 2.7 V, DAC at full-scale | –1 | 1 | %FSR | ||
2.7 V ≤ VDD ≤ 5.5 V, DAC at full-scale | –0.5 | 0.5 | ||||
Full-scale-error temperature coefficient(4) | DAC at full-scale | ±0.0008 | %FSR/°C | |||
OUTPUT | ||||||
Output voltage | Reference tied to VDD | 0 | VDD | V | ||
CL | Capacitive load(2) | RL = infinite, phase margin = 30° | 200 | pF | ||
Phase margin = 30° | 1000 | |||||
Short-circuit current | VDD = 1.7 V, full-scale output shorted to AGND or zero-scale output shorted to VDD |
15 | mA | |||
VDD = 2.7 V, full-scale output shorted to AGND or zero-scale output shorted to VDD |
50 | |||||
VDD = 5.5 V, full-scale output shorted to AGND or zero-scale output shorted to VDD |
60 | |||||
Output-voltage headroom(2) | To VDD (DAC output unloaded, internal reference = 1.21 V), VDD ≥ 1.21 V ☓ gain + 0.2 V |
0.2 | V | |||
To VDD and AGND (DAC output unloaded, external reference at VDD, gain = 1x, the VREF pin is not shorted to VDD) | 0.8 | %FSR | ||||
To VDD and AGND (ILOAD = 10 mA at VDD = 5.5 V, ILOAD = 3 mA at VDD = 2.7 V, ILOAD = 1 mA at VDD = 1.8 V), external reference at VDD, gain = 1x, the VREF pin is not shorted to VDD |
10 | |||||
ZO | VFB dc output impedance(3) | DAC output enabled, internal reference (gain = 1.5x or 2x) or external reference at VDD (gain = 1x), the VREF pin is not shorted to VDD | 400 | 500 | 600 | kΩ |
DAC output enabled, internal VREF, gain = 3x or 4x | 325 | 400 | 485 | |||
Power supply rejection ratio (dc) | Internal VREF, gain = 2x, DAC at midscale, VDD = 5 V ±10% | 0.25 | mV/V | |||
DYNAMIC PERFORMANCE | ||||||
tsett | Output voltage settling time | 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V |
20 | µs | ||
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V, internal VREF, gain = 4x |
25 | |||||
Slew rate | VDD = 5.5 V | 0.3 | V/µs | |||
Power-on glitch magnitude | At startup (DAC output disabled) | 75 | mV | |||
At startup (DAC output disabled), RL = 100 kΩ | 200 | |||||
Output-enable glitch magnitude | DAC output disabled to enabled (DAC registers at zero scale), RL = 100 kΩ | 250 | mV | |||
Vn | Output noise voltage (peak to peak) | f = 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V | 50 | µVPP | ||
Internal VREF, gain = 4x, f = 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V |
90 | |||||
Output noise density | f = 1 kHz, DAC at midscale, VDD = 5.5 V | 0.35 | µV/√Hz | |||
Internal VREF, gain = 4x, f = 1 kHz, DAC at midscale, VDD = 5.5 V |
0.9 | |||||
Power supply rejection ratio (ac)(3) | Internal VREF, gain = 4x, 200-mV 50-Hz or 60-Hz sine wave superimposed on power supply voltage, DAC at midscale | -68 | dB | |||
Code change glitch impulse | ±1 LSB change around midscale (including feedthrough) | 10 | nV-s | |||
Code change glitch impulse magnitude | ±1 LSB change around midscale (including feedthrough) | 15 | mV | |||
POWER | ||||||
IDD | Current flowing into VDD(4) (5) | Normal operation, DACs at full scale, digital pins static, external reference at VDD but the VREF pin is not shorted to VDD | 35 | 50 | µA/ch |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
STATIC PERFORMANCE | ||||||
Resolution | 8 | Bits | ||||
INL | Integral nonlinearity | DAC codes between 10d and 255d for current output range of 0 µA to 25 µA, DAC codes between 0d and 255d for other ranges | –1 | 1 | LSB | |
DNL | Differential nonlinearity | DAC codes between 10d and 255d for current output range of 0 µA to 25 µA, DAC codes between 0d and 255d for other ranges | –1 | 1 | LSB | |
Offset error | DAC output range: 0 µA to 25 µA, DAC at code 10d | ±1.5 | %FSR | |||
DAC output ranges: 0 µA to 50 µA, 0 µA to 125 µA, and 0 µA to 250 µA; DAC at zero-scale | 5 | |||||
all unipolar negative ranges, DAC at zero-scale | -5 | |||||
DAC output ranges: ±25 µA, ±50 µA, ±125 µA, and ±250 µA; DAC at midscale | ±1 | |||||
Gain error | DAC output range: 0 µA to 25 µA, DAC codes between 10d and 255d | ±1.5 | %FSR | |||
DAC output ranges: 0 µA to 50 µA, 0 µA to 125 µA, and 0 µA to 250 µA; DAC codes between 0d and 255d | ±1.5 | |||||
all unipolar negative ranges, DAC codes between 0d and 255d | ±5 | |||||
DAC output ranges: ±25 µA, ±50 µA, ±125 µA, and ±250 µA; DAC codes between 0d and 255d | ±1.3 | |||||
OUTPUT | ||||||
Output compliance voltage(1) | DAC output range: 0 µA to 25 µA, to VDD and to AGND | 200 | mV | |||
DAC output ranges: 0 µA to 50 µA, 0 µA to 125 µA, and 0 µA to 250 µA; to VDD | 400 | |||||
all unipolar negative ranges, to VDD | 400 | |||||
DAC output ranges: ±25 µA, ±50 µA, ±125 µA, and ±250 µA; to VDD and to AGND | 400 | |||||
ZO | IOUT dc output impedance(2) | DAC at midscale, DAC output kept at VDD/2 | 60 | MΩ | ||
Power supply rejection ratio (dc) | DAC at midscale, output range: 0 µA to 25 µA, VDD changed from 4.5 V to 5.5 V | 0.28 | LSB/V | |||
DAC at midscale, all unipolar positive ranges, VDD changed from 4.5 V to 5.5V | 0.33 | |||||
DAC at midscale, all unipolar negative ranges, VDD changed from 4.5 V to 5.5V | 0.83 | |||||
DAC at midscale, all bipolar ranges, VDD changed from 4.5V to 5.5V | 0.23 | |||||
DYNAMIC PERFORMANCE | ||||||
tsett | Output current settling time | 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 1 LSB at 8-bit resolution, VDD = 5.5 V, common-mode voltage at OUTx pin is VDD/2 | 60 | µs | ||
Vn | Output noise current (peak to peak) | 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V, ±250-µA output range |
150 | nAPP | ||
Output noise density | f = 1 kHz, DAC at midscale, VDD = 5.5 V, ±250-µA output range |
1 | nA/√Hz | |||
Power supply rejection ratio (ac)(3) | ±250 µA output range, 200-mV 50-Hz or 60-Hz sine wave superimposed on power-supply voltage, DAC at midscale | 0.65 | LSB/V | |||
POWER | ||||||
IDD | Current flowing into VDD(3) (4) | Normal operation, DACs at midscale, all unipolar output ranges, digital pins static | 18 | 24 | µA/ch | |
Normal operation, DACs at full scale, ±25-µA output range, digital pins static | 42 | 50 | ||||
Normal operation, DACs at full scale, ±50-µA output range, digital pins static | 56 | 70 | ||||
Normal operation, DACs at full scale, ±125-µA output range, digital pins static | 98 | 120 | ||||
Normal operation, DACs at full scale, ±250-µA output range, digital pins static | 167 | 200 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
STATIC PERFORMANCE | ||||||
Offset error(1) (2) | 1.7 V ≤ VDD ≤ 5.5 V, DAC at midscale, comparator input at Hi-Z, and DAC operating with external reference | –5 | 0 | 5 | mV | |
Offset error time drift(1) | VDD = 5.5 V, external reference, TA = 125°C, FBx in Hi-Z mode, DAC at full scale and VFB at 0 V or DAC at zero scale and VFB at 1.84 V, drift specified for 10 years of continuous operation | 4 | mV | |||
OUTPUT | ||||||
Input voltage | VREF connected to VDD, FBx resistor network connected to ground | 0 | VDD | V | ||
VREF connected to VDD, FBx resistor network disconnected from ground | 0 | VDD (1/3 – 1/100) | ||||
VOL | Logic low output voltage | ILOAD = 100 μA, output in open-drain mode | 0.1 | V | ||
DYNAMIC PERFORMANCE | ||||||
tresp | Output response time | DAC at midscale with 10-bit resolution, FBx input at Hi-Z, and transition step at FBx node is (VDAC – 2 LSB) to (VDAC + 2 LSB), transition time measured between 10% and 90% of output, output current of 100 µA, comparator output configured in push-pull mode, load capacitor at DAC output is 25 pF | 10 | µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INTERNAL REFERENCE | ||||||
Initial accuracy | TA = 25°C | 1.1979 | 1.212 | 1.224 | V | |
Reference output temperature coefficient(1) (2) | 50 | ppm/°C | ||||
EXTERNAL REFERENCE | ||||||
VREF input impedance(1) (3) | 192 | kΩ/ch | ||||
EEPROM | ||||||
Endurance(1) | –40°C ≤ TA ≤ +85°C | 20000 | Cycles | |||
TA = 125°C | 1000 | |||||
Data retention(1) | TA = 25°C | 50 | Years | |||
EEPROM programming write cycle time(1) | 200 | ms | ||||
Device boot-up time(1) | Time taken from power valid (VDD ≥ 1.7 V) to output valid state (output state as programmed in EEPROM), 0.5-µF capacitor on the CAP pin | 5 | ms | |||
DIGITAL INPUTS | ||||||
Digital feedthrough | Voltage output mode, DAC output static at midscale, fast mode plus, SCL toggling | 20 | nV-s | |||
Pin capacitance | Per pin | 10 | pF | |||
POWER-DOWN MODE | ||||||
IDD | Current flowing into VDD(1) | DAC in sleep mode, internal reference powered down, external reference at 5.5 V | 28 | µA | ||
DAC in sleep mode, internal reference enabled, additional current through internal reference | 10 | |||||
DAC channels enabled, internal reference enabled, additional current through internal reference per DAC channel in voltage-output mode | 12.5 | |||||
Current flowing into VDD | DAC in deep-sleep mode, internal reference powered down, SDO mode disabled | 1.5 | 3 | |||
HIGH-IMPEDANCE OUTPUT | ||||||
ILEAK | Current flowing into VOUTX and VFBX | DAC in Hi-Z output mode, 1.7 V ≤ VDD ≤ 5.5 V | 10 | nA | ||
VDD = 0 V, VOUT ≤ 1.5 V, decoupling capacitor between VDD and AGND = 0.1 μF | 200 | |||||
VDD = 0 V, 1.5 V < VOUT ≤ 5.5 V, decoupling capacitor between VDD and AGND = 0.1 μF | 500 | |||||
100 kΩ between VDD and AGND, VOUT ≤ 1.25 V, series resistance of 10 kΩ at OUTx pin | ±2 | µA |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCL frequency | 100 | kHz | ||
tBUF | Bus free time between stop and start conditions | 4.7 | µs | ||
tHDSTA | Hold time after repeated start | 4 | µs | ||
tSUSTA | Repeated start setup time | 4.7 | µs | ||
tSUSTO | Stop condition setup time | 4 | µs | ||
tHDDAT | Data hold time | 0 | ns | ||
tSUDAT | Data setup time | 250 | ns | ||
tLOW | SCL clock low period | 4700 | ns | ||
tHIGH | SCL clock high period | 4000 | ns | ||
tF | Clock and data fall time | 300 | ns | ||
tR | Clock and data rise time | 1000 | ns | ||
tVD_DAT | Data valid time | 3.45 | µs | ||
tVD_ACK | Data valid acknowledge time | 3.45 | µs |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCL frequency | 400 | kHz | ||
tBUF | Bus free time between stop and start conditions | 1.3 | µs | ||
tHDSTA | Hold time after repeated start | 0.6 | µs | ||
tSUSTA | Repeated start setup time | 0.6 | µs | ||
tSUSTO | Stop condition setup time | 0.6 | µs | ||
tHDDAT | Data hold time | 0 | ns | ||
tSUDAT | Data setup time | 100 | ns | ||
tLOW | SCL clock low period | 1300 | ns | ||
tHIGH | SCL clock high period | 600 | ns | ||
tF | Clock and data fall time | 300 | ns | ||
tR | Clock and data rise time | 300 | ns | ||
tVD_DAT | Data valid time | 0.9 | µs | ||
tVD_ACK | Data valid acknowledge time | 0.9 | µs |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCL frequency | 1 | MHz | ||
tBUF | Bus free time between stop and start conditions | 0.5 | µs | ||
tHDSTA | Hold time after repeated start | 0.26 | µs | ||
tSUSTA | Repeated start setup time | 0.26 | µs | ||
tSUSTO | Stop condition setup time | 0.26 | µs | ||
tHDDAT | Data hold time | 0 | ns | ||
tSUDAT | Data setup time | 50 | ns | ||
tLOW | SCL clock low period | 0.5 | µs | ||
tHIGH | SCL clock high period | 0.26 | µs | ||
tF | Clock and data fall time | 120 | ns | ||
tR | Clock and data rise time | 120 | ns | ||
tVD_DAT | Data valid time | 0.45 | µs | ||
tVD_ACK | Data valid acknowledge time | 0.45 | µs |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
f(SCLK) | Serial clock frequency | 50 | MHz | ||
tSCLKHIGH | SCLK high time | 9 | ns | ||
tSCLKLOW | SCLK low time | 9 | ns | ||
tSDIS | SDI setup time | 8 | ns | ||
tSDIH | SDI hold time | 8 | ns | ||
tCSS | CS to SCLK falling edge setup time | 18 | ns | ||
tCSH | SCLK falling edge to CS rising edge | 10 | ns | ||
tCSHIGH | CS hight time | 50 | ns | ||
tDACWAIT | Sequential DAC update wait time for same channel | 2 | µs | ||
tBCASTWAIT | Broadcast DAC update wait time | 2 | µs |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
f(SCLK) | Serial clock frequency | 1.25 | MHz | ||
tSCLKHIGH | SCLK high time | 350 | ns | ||
tSCLKLOW | SCLK low time | 350 | ns | ||
tSDIS | SDI setup time | 8 | ns | ||
tSDIH | SDI hold time | 8 | ns | ||
tCSS | SYNC to SCLK falling edge setup time | 400 | ns | ||
tCSH | SCLK falling edge to SYNC rising edge | 400 | ns | ||
tCSHIGH | SYNC hight time | 1 | µs | ||
tSDODLY | SCLK rising edge to SDO falling edge, IOL ≤ 5 mA, CL = 20 pF. | 300 | ns |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
f(SCLK) | Serial clock frequency | 2.5 | MHz | ||
tSCLKHIGH | SCLK high time | 175 | ns | ||
tSCLKLOW | SCLK low time | 175 | ns | ||
tSDIS | SDI setup time | 8 | ns | ||
tSDIH | SDI hold time | 8 | ns | ||
tCSS | SYNC to SCLK falling edge setup time | 300 | ns | ||
tCSH | SCLK falling edge to SYNC rising edge | 300 | ns | ||
tCSHIGH | SYNC hight time | 1 | µs | ||
tSDODLY | SCLK rising edge to SDO falling edge, IOL ≤ 5 mA, CL = 20 pF. | 300 | ns |