SBAS528D June   2013  – December 2021 DAC7760 , DAC8760

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: AC
    7. 7.7  Timing Requirements: Write Mode
    8. 7.8  Timing Requirements: Readback Mode
    9. 7.9  Timing Diagrams
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  DAC Architecture
      2. 8.3.2  Voltage Output Stage
      3. 8.3.3  Current Output Stage
      4. 8.3.4  Internal Reference
      5. 8.3.5  Digital Power Supply
      6. 8.3.6  DAC Clear
      7. 8.3.7  Power-On Reset
      8. 8.3.8  Alarm Detection
      9. 8.3.9  Watchdog Timer
      10. 8.3.10 Frame Error Checking
      11. 8.3.11 User Calibration
      12. 8.3.12 Programmable Slew Rate
    4. 8.4 Device Functional Modes
      1. 8.4.1 Setting Voltage and Current Output Ranges
      2. 8.4.2 Boost Configuration for IOUT
      3. 8.4.3 Filtering the Current Output (only on the VQFN package)
      4. 8.4.4 HART Interface
        1. 8.4.4.1 For 4-mA to 20-mA Mode
        2. 8.4.4.2 For All Current Output Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI)
        1. 8.5.1.1 SPI Shift Register
        2. 8.5.1.2 Write Operation
        3. 8.5.1.3 Read Operation
        4. 8.5.1.4 Stand-Alone Operation
        5. 8.5.1.5 Multiple Devices on the Bus
    6. 8.6 Register Maps
      1. 8.6.1 DACx760 Command and Register Map
        1. 8.6.1.1 DACx760 Register Descriptions
          1. 8.6.1.1.1 Control Register
          2. 8.6.1.1.2 Configuration Register
          3. 8.6.1.1.3 DAC Registers
          4. 8.6.1.1.4 Reset Register
          5. 8.6.1.1.5 Status Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Controlling the VOUT and IOUT Pins
        1. 9.1.1.1 VOUT and IOUT Pins are Independent Outputs, Never Simultaneously Enabled
        2. 9.1.1.2 VOUT and IOUT Pins are Independent Outputs, Simultaneously Enabled
        3. 9.1.1.3 VOUT and IOUT Pins are Tied Together, Never Simultaneously Enabled
      2. 9.1.2 Implementing HART in All Current Output Modes
        1. 9.1.2.1 Using CAP2 Pin on VQFN Package
        2. 9.1.2.2 Using the ISET-R Pin
      3. 9.1.3 Short-Circuit Current Limiting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

at AVDD = 10 V to 36 V, AVSS = –18 V to 0 V, AVDD + |AVSS| ≤ 36 V, GND = 0 V, REFIN = 5-V external, and DVDD = 2.7 V to 5.5 V; for VOUT: RL = 1 kΩ, CL = 200 pF; for IOUT: RL = 300 Ω; all specifications are from TA = –40°C to +125°C (unless otherwise noted); typical specifications are at 25°C
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VOLTAGE OUTPUT
Voltage output ranges (normal mode)AVDD ≥ 10 V05V
AVDD ≥ 10.5 V010
AVSS ≤ –5.5 V, AVDD ≥ 10 V–55
AVSS ≤ –10.5 V, AVDD ≥ 10.5 V–1010
Voltage output range (overrange mode)AVDD ≥ 10 V05.5V
AVDD ≥ 11.5 V011
AVSS ≤ –6 V, AVDD ≥ 10 V–5.55.5
AVSS ≤ –11.5 V, AVDD ≥ 11.5 V–1111
ResolutionDAC876016Bits
DAC776012
ACCURACY(2)
Total unadjusted error, TUETA = –40°C to 125°C–0.07%0.07%FSR
TA = –40°C to +85°C–0.06%0.06%
TA = 25°C–0.04%±0.015%0.04%
Differential nonlinearity, DNLMonotonic±1LSB
Relative accuracy, INLTA = –40°C to 125°C±0.04%FSR
TA = –40°C to +85°C±0.022%
Bipolar zero errorTA = –40°C to 125°C–77mV
TA = –40°C to +85°C–66
TA = 25°C, ±5 V and ±5.5 V–1.5±0.51.5
TA = 25°C, ±10 V and ±11 V–3±13
Bipolar zero error temperature coefficient±1ppm FSR/°C
Zero-scale error(3)Unipolar range (0 V to 5 V, 0 V to 5.5 V, 0 V to 10 V, 0 V to 11 V)TA = –40°C to 125°C–44mV
TA = –40°C to +85°C–22
TA = 25°C–0.6±0.10.6
Bipolar range (±5 V, ±5.5 V, ±10 V, ±11 V)TA = –40°C to 125°C–1010mV
TA = 25°C–3.5±13.5
Zero-scale error temperature coefficient±2ppm FSR/°C
Offset errorTA = –40°C to 125°C, unipolar range–44mV
TA = –40°C to +85°C, unipolar range–22
TA = 25°C, unipolar range–0.6±0.10.6
ACCURACY (continued)
Offset error temperature coefficient±1ppm FSR/°C
Gain errorTA = –40°C to 125°C–0.07%0.07%FSR
TA = –40°C to +85°C–0.06%0.06%
TA = 25°C–0.04%±0.01%0.04%
Gain error temperature coefficient±3ppm FSR/°C
Full-scale errorTA = –40°C to 125°C–0.07%0.07%FSR
TA = –40°C to +85°C–0.06%0.06%
TA = 25°C–0.04%±0.01%0.04%
Full-scale error temperature coefficient±1ppm FSR/°C
VOLTAGE OUTPUT (UNIPOLAR AND BIPOLAR MODES)
HeadroomAVDD with respect to VOUT full scale0.5V
FootroomAVSS with respect to VOUT zero scale–0.5V
Output voltage drift vs timeTA = 125°C, 1000 hrs±15ppm FSR
Short-circuit current30mA
LoadFor specified performance1kΩ
Capacitive load stability(4)RL = ∞20nF
RL = 1 kΩ5nF
RL = 1 kΩ, external compensation capacitor (4 nF) connected1µF
DC output impedanceCode = 0x80000.3Ω
DC PSRR(4)No output load310µV/V
CURRENT OUTPUT
Output current rangesRANGE bits = 111024mA
RANGE bits = 110020
RANGE bits = 101420
ResolutionDAC876016Bits
DAC776012
ACCURACY (0-mA to 20-mA and 0-mA to 24-mA Range)(1)
Total unadjusted error, TUETA = –40°C to +125°C–0.2%0.2%FSR
TA = –40°C to +85°C–0.16%0.16%
TA = 25°C–0.08%±0.02%0.08%
Differential nonlinearity, DNLMonotonic±1LSB
Relative accuracy, INL(5)TA = –40°C to +125°C±0.08%FSR
TA = –40°C to +85°C±0.024%
Offset errorTA = –40°C to +125°C–0.17%0.17%FSR
TA = –40°C to +85°C–0.1%0.1%
TA = 25°C–0.07%±0.01%0.07%
Offset error temperature coefficient±5ppm FSR/°C
Full-scale errorTA = –40°C to +125°C–0.2%0.2%FSR
TA = –40°C to +85°C–0.16%0.16%
TA = 25°C–0.08%±0.015%0.08%
Full-scale error temperature coefficientInternal RSET±5ppm FSR/°C
External RSET±10
ACCURACY (0-mA to 20-mA and 0-mA to 24-mA Range) (continued)
Gain errorInternal RSETTA = –40°C to +125°C–0.2%0.2%FSR
TA = –40°C to +85°C–0.15%0.15%
TA = 25°C–0.08%±0.01%0.08%
External RSETTA = –40°C to +125°C–0.17%0.17%
TA = –40°C to +85°C–0.12%0.12%
TA = 25°C–0.05%±0.01%0.05%
Gain error temperature coefficientInternal RSET±3ppm FSR/°C
External RSET±8
Output current drift vs timeTA = +125°C, 1000 hrsInternal RSET±50ppm FSR
External RSET±25
ACCURACY (4-mA TO 20-mA RANGE)(1)
Total unadjusted error, TUEInternal RSETTA = –40°C to +125°C–0.25%0.25%FSR
TA = 25°C–0.08%±0.02%0.08%
External RSETTA = –40°C to +125°C–0.29%0.29%
TA = –40°C to +85°C–0.25%0.25%
TA = 25°C–0.1%±0.02%0.1%
Differential nonlinearity, DNLMonotonic±1LSB
Relative accuracy, INL(5)TA = –40°C to +125°C±0.08%FSR
TA = –40°C to +85°C±0.024%
Offset errorInternal RSETTA = –40°C to +125°C–0.22%0.22%FSR
TA = –40°C to +85°C–0.2%0.2%
External RSETTA = –40°C to +125°C–0.2%0.2%
TA = –40°C to +85°C–0.18%0.18%
Internal and External RSET, TA = 25°C–0.07%±0.01%0.07%
Offset error temperature coefficient±3ppm FSR/°C
Full-scale errorInternal RSETTA = –40°C to +125°C–0.25%0.25%FSR
TA = 25°C–0.08%±0.015%0.08%
External RSETTA = –40°C to +125°C–0.29%0.29%
TA = –40°C to +85°C–0.25%0.25%
TA = 25°C–0.1%±0.015%0.1%
Full-scale error temperature coefficientInternal RSET±5ppm FSR/°C
External RSET±10
Gain errorInternal RSETTA = –40°C to +125°C–0.2%0.2%FSR
TA = –40°C to +85°C–0.15%0.15%
TA = 25°C–0.08%±0.01%0.08%
External RSETTA = –40°C to +125°C–0.16%0.16%
TA = –40°C to +85°C–0.12%0.12%
TA = 25°C–0.05%±0.01%0.055%
Gain error temperature coefficientInternal RSET±3ppm FSR/°C
External RSET±8
Output current drift vs timeTA = 125°C, 1000 hrsInternal RSET±50ppm FSR
External RSET±75
CURRENT OUTPUT(4)
Inductive load50mH
DC PSRR1µA/V
Output impedanceCode = 0x800050MΩ
EXTERNAL REFERENCE INPUT
Reference input capacitance10pF
INTERNAL REFERENCE OUTPUT
Reference outputTA = 25°C4.9955.005V
Reference temperature coefficient(4)TA = –40°C to +85°C±10ppm/°C
Output noise (0.1 Hz to 10 Hz)TA = 25°C14µVPP
Noise spectral densityTA = 25°C, 10 kHz185nV/√ Hz
Capacitive load600nF
Load current±5mA
Short-circuit current (REFOUT shorted to GND)25mA
Load regulationAVDD = 24 V, AVSS = 0 V, TA = 25°C, sourcing55µV/mA
AVDD = 24 V, AVSS = 0 V, TA = 25°C, sinking120
Line regulation±1.2µV/V
DVDD INTERNAL REGULATOR
Output voltageAVDD = 24 V4.6V
Output load current(4)10mA
Load regulation3.5mV/mA
Line regulation1mV/V
Short-circuit currentAVDD = 24 V, to GND35mA
Capacitive load stability(4)2.5µF
DIGITAL INPUTS
Hysteresis voltage0.4V
Input currentDVDD-EN, VIN ≤ 5 V–2.7µA
All pins other than DVDD-EN±1µA
Pin capacitancePer pin10pF
DIGITAL OUTPUTS
SDOVOL, output low voltage, sinking 200 µA0.4V
VOH, output high voltage, sourcing 200 µADVDD – 0.5V
High-impedance leakage±1µA
ALARMVOL, output low voltage, 10-kΩ pullup resistor to DVDD0.4V
VOL, output low voltage, 2.5 mA0.6V
High-impedance leakage±1µA
High-impedance output capacitance10pF
POWER REQUIREMENTS
AIDDOutputs disabled, external DVDD3mA
Outputs disabled, internal DVDD4
Code = 0x8000, VOUT enabled, unloaded4.6
Code = 0x0000, IOUT enabled3
Code = 0x0000, both outputs enabled, VOUT unloaded4.6
AISSOutputs disabled0.6mA
Outputs disabled, Internal DVDD0.6
Code = 0x8000, VOUT enabled, unloaded2.6
Code = 0x0000, IOUT enabled0.6
Code = 0x0000, both outputs enabled, VOUT unloaded2.6
DIDDVIH = DVDD, VIL = GND, interface idle1mA
Power dissipationAVDD = 36 V, AVSS = GND, VOUT enabled, unloaded, DVDD = 5 V140170mW
AVDD = 18 V, AVSS = –18 V, VOUT enabled, unloaded, DVDD = 5 V135
TEMPERATURE
Thermal alarm142°C
Thermal alarm hysteresis18°C
(1) DAC8760 and DAC7760 current output range is set by writing to RANGE bits in control register at address 0x55.
(2) When powered with AVSS = 0 V, INL and offset error for the 0-V to 5-V and 0-V to 10-V ranges are calculated beginning from code 0x0100 for DAC8760 and from code 0x0010 for DAC7760.
(3) Assumes a footroom of 0.5 V.
(4) Specified by design and characterization; not production tested.
(5) For 0-mA to 20-mA and 0-mA to 24-mA ranges, INL is calculated beginning from code 0x0100 for DAC8760 and from code 0x0010 for DAC7760.