SLAS464C December   2006  – January 2018 DAC8560

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Functional Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Typical Characteristics: Internal Reference
    8. 6.8  Typical Characteristics: DAC at VDD = 5 V
    9. 6.9  Typical Characteristics: DAC at VDD = 3.6 V
    10. 6.10 Typical Characteristics: DAC at VDD = 2.7 V
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC)
      2. 7.3.2 Resistor String
      3. 7.3.3 Output Amplifier
      4. 7.3.4 DAC Noise Performance
      5. 7.3.5 Internal Reference
        1. 7.3.5.1 Enable/Disable Internal Reference
        2. 7.3.5.2 Internal Reference Load
          1. 7.3.5.2.1 Supply Voltage
          2. 7.3.5.2.2 Temperature Drift
          3. 7.3.5.2.3 Noise Performance
          4. 7.3.5.2.4 Load Regulation
          5. 7.3.5.2.5 Long-Term Stability
          6. 7.3.5.2.6 Thermal Hysteresis
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Down Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Input Shift Register
      3. 7.5.3 SYNC Interrupt
      4. 7.5.4 Power-On Reset
    6. 7.6 Register Maps
      1. 7.6.1 Write Sequence for Disabling the DAC8560 Internal Reference
        1. Table 1. Write Sequence for Disabling the DAC8560 Internal Reference
      2. 7.6.2 Enabling the DAC8560 Internal Reference (Write Sequence 1 of 2)
        1. Table 2. Enabling the DAC8560 Internal Reference (Write Sequence 1 of 2)
      3. 7.6.3 Enabling the DAC8560 Internal Reference (Write Sequence 2 of 2)
        1. Table 3. Enabling the DAC8560 Internal Reference (Write Sequence 2 of 2)
      4. 7.6.4 DAC8560 Data Input Register Format
        1. Table 4. DAC8560 Data Input Register Format
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure or Bipolar Operation > ±VREF
        1. 8.2.2.1 Bipolar Operation Greater Than ±VREF
          1. 8.2.2.1.1 Passive Component Selection
          2. 8.2.2.1.2 Amplifier Selection
        2. 8.2.2.2 Microprocessor Interfacing
          1. 8.2.2.2.1 DAC8560 to 8051 Interface
          2. 8.2.2.2.2 DAC8560 to Microwire Interface
          3. 8.2.2.2.3 DAC8560 to 68HC11 Interface
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resource
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.1.1 Passive Component Selection

The amplifier in this circuit uses negative feedback to ensure that the voltages at the inverting and non-inverting terminals are equal. When the DAC output is at zero scale (0 V) the inverting terminal is a virtual ground so no current flows across RG1; this causes the circuit to function as an inverting amplifier with gain equal to RFB / RG2. When the DAC output is full-scale (VREF) the inverting terminal potential is equal to VREF so no current flows across RG2; this causes the circuit to function as a non-inverting amplifier with gain equal to (1 + RFB / RG1). A simple three-step process can be used to select the resistor values used to realize any bipolar output range using DAC8560. The internal VREF value is 2.5 V. The desired output range for this design is ±10 V. First, using the transfer function shown in Equation 6, consider the negative full-scale output case when VDAC is equal to 0 V, VREF is equal to 2.5 V, and VOUT is equal to –10 V. This case is used to calculate the ratio of RFB to RG2 and is shown explicitly in Equation 7.

Equation 7. DAC8560 rfb-to-rg2-ratio.gif

Second, consider the positive full-scale output case when VDAC is equal to 2.5 V, VREF is equal to 2.5 V, and VOUT is equal to 10 V. This case is used to calculate the ratio of RFB to RG1 and is shown explicitly in Equation 8.

Equation 8. DAC8560 rfb-to-rg1-ratio.gif

Finally, seed the ideal value of RG2 to calculate the ideal values of RFB and RG2. The key considerations for seeding the value of RG2 should be the drive strength of the reference source as well as choosing small resistor values to minimize noise contributed by the resistor network. For this design RG2 of 8.25 kΩ was chosen, which limits the peak current drawn from the reference source to approximately 333 µA under nominal conditions, well within the 20-mA limit of the DAC8560. In this case the nearest, 0.1% tolerance, 0603 package values for each resistor are ideal.

Standard values for 0.1% resistors can be an obstacle for this design and it may take multiple iterations of seeding the values to find real components or they may not exist. Workarounds can include utilizing multiple resistors in series and/or parallel, using potentiometers for analog trim calibration, or providing extra gain in the output circuit and applying digital calibration. In systems where the output voltage must reach the design-goal end-points (±10 V) it may be desirable to apply additional gain to the circuit. This approach may contribute additional overall system error since the end-point errors vary from system to system. For this design, use the exact values calculated in the design process to keep error analysis easy to follow.

To deliver a near-universal cable drive solution, choose CLOAD to be relatively large compared to typical cable capacitance such that its capacitance dominates the reactive load seen by the output amplifier. To drive larger capacitive loads RISO, CCOMP, and CLOAD may need to be adjusted. An RISO of 70 Ω and CCOMP of 150 pF are used for this design.

Resistor matching for the op amp resistor network is critical for the success of this design; choose components with tight tolerances. For this design 0.1% resistor values are implemented but this constraint may be adjusted based on application specific design goals. Resistor matching contributes to both offset error and gain error in this design. The tolerance of stability components RISO and CCOMP is not critical and 1% components are acceptable.

Table 3. Values of Resistor Network

RESISTOR VALUE
RG1 11 kΩ
RG2 8.25 kΩ
RFB 33 kΩ