SBAS528D June 2013 – December 2021 DAC7760 , DAC8760
PRODUCTION DATA
The DAC has an asynchronous clear function through the CLR pin, which is active-high and allows the voltage output to be cleared to either zero-scale code or midscale code. This action is user-selectable through the CLR-SEL pin or the CLRSEL bit of Table 8-17, as Table 8-2 describes. The CLR-SEL pin and CLRSEL register are ORed together. The current output clears to the bottom of its preprogrammed range. When the CLR signal returns to low, the output remains at the cleared value. The pre-clear value can be restored by pulsing the LATCH signal without clocking any data. A new value cannot be programmed until the CLR pin returns to low. Note that in dual-output mode, the value that the DAC data register is cleared to follows the settings for the voltage output mode.
CLR-SEL | OUTPUT VALUE | |
---|---|---|
UNIPOLAR OUTPUT RANGE | BIPOLAR OUTPUT RANGE | |
0 | 0 V | 0 V |
1 | Midscale | Negative full-scale |
In addition to defining the output value for a clear operation, the CLRSEL bit and the CLR-SEL pin also define the default output value. During the selection of a new voltage range, the output value corresponds to the definitions given in Table 8-7. To avoid glitches on the output, disable the output by writing a 0 to the OUTEN bit of Table 8-17 before changing the voltage range. When the OUTEN bit is set to 1, the output goes to the default value as defined by the CLRSEL bit and the CLR-SEL pin.