SBAS349F August   2005  – June 2016 DAC8812

PRODUCTION DATA.  

  1. 1  Features
  2. 2  Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
      1. 7.8.1 Channel A—5 V
      2. 7.8.2 Channel B—5 V
      3. 7.8.3 Channel A and B—5 V
      4. 7.8.4 Channel A—2.7 V
      5. 7.8.5 Channel B—2.7 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converters
      2. 8.3.2 Power-On Reset
        1. 8.3.2.1 ESD Protection Circuits
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Data Interface
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

PW Package
16-Pin TSSOP
Top View

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 RFBA I Establish voltage output for DAC A by connecting to external amplifier output.
2 VREFA I DAC A reference voltage input pin. Establishes DAC A full-scale output voltage. Can be tied to VDD pin.
3 IOUTA O DAC A current output
4 AGNDA — DAC A analog ground
5 AGNDB — DAC B analog ground
6 IOUTB O DAC B current output
7 VREFB I DAC B reference voltage input pin. Establishes DAC B full-scale output voltage. Can be tied to VDD pin.
8 RFBB I Establish voltage output for DAC B by connecting to external amplifier output.
9 SDI I Serial data input; data loads directly into the shift register.
10 RS I Reset pin; active-low input. Input registers and DAC registers are set to all 0s or midscale. Register data = 0x0000 when MSB = 0. Register data = 0x8000 when MSB = 1 for DAC8812.
11 CS I Chip-select; active-low input. Disables shift register loading when high. Transfers serial register data to input register when CS goes high. Does not affect LDAC operation.
12 DGND — Digital ground
13 VDD I Positive power-supply input. Specified range of operation 2.7 V to 5.5 V.
14 MSB I MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system power-on. Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can be permanently tied to ground or VDD.
15 LDAC I Load DAC register strobe; level-sensitive active-low. Transfers all input register data to the DAC registers. Asynchronous active-low input. See Table 2 for operation.
16 CLK I Clock input. Positive edge clocks data into shift register.