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  • DIX4192 Integrated Digital Audio Interface Receiver and Transmitter

    • SBFS031F February   2006  – September 2016 DIX4192

      PRODUCTION DATA.  

  • CONTENTS
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  • DIX4192 Integrated Digital Audio Interface Receiver and Transmitter
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 RESET Operation
      2. 9.3.2 Master and Reference Clocks
      3. 9.3.3 Audio Serial Port Operation
      4. 9.3.4 Overview of the AES3 Digital Audio Interface Protocol
      5. 9.3.5 Digital Interface Transmitter (DIT) Operation
      6. 9.3.6 Digital Interface Receiver (DIR) Operation
      7. 9.3.7 General-Purpose Digital Outputs
      8. 9.3.8 Interrupt Output
    4. 9.4 Device Functional Modes
      1. 9.4.1 Host Interface Operation: Serial Peripheral Interface (SPI) Mode
      2. 9.4.2 Host Interface Operation: PHILIPS I2C Mode
    5. 9.5 Register Maps
      1. 9.5.1 Register and Data Buffer Organization
      2. 9.5.2 Control Registers
        1. 9.5.2.1 Registers 1F through 28: Q-Channel Sub-Code Data Registers
        2. 9.5.2.2 Registers 29 through 2C: IEC61937 PC/PD Burst Preamble
      3. 9.5.3 Channel Status and User Data Buffer Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Digital Audio Transformer Vendors
      2. 10.1.2 Receiver Input Interfacing
      3. 10.1.3 Transmitter Output Interfacing
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Differential Line Inputs and Output
        2. 10.2.2.2 Serial Ports
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
  15. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • PFB|48
    • MTQF019B
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • sbfs031f_oa
  • sbfs031f_pm
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DATA SHEET

DIX4192 Integrated Digital Audio Interface Receiver and Transmitter

1 Features

  • Digital Audio Interface Transmitter (DIT)
    • Supports Sampling Rates Up to 216 kHz
    • Includes Differential Line Driver and
      CMOS-Buffered Outputs
  • Digital Audio Interface Receiver (DIR)
    • PLL Lock Range Includes Sampling Rates from 20 kHz to 216 kHz
    • Four Differential-Input Line Receivers and an Input Multiplexer
    • Bypass Multiplexer Routes Line Receiver Outputs to Line Driver and Buffer Outputs
    • Automatic Detection of Non-PCM Audio Streams (DTS CD/LD and IEC 61937 formats)
    • Audio CD Q-Channel Sub-Code Decoding and Data Buffer
    • Low Jitter Recovered Clock Output
  • User-Selectable Serial Host Interface: SPI™ or I2C
    • Provides Access to On-Chip Registers and Data Buffers
    • Status Registers and Interrupt Generation for Flag and Error Conditions
    • Block-Sized Data Buffers for Both Channel Status and User Data
  • Two Audio Serial Ports (Ports A and B)
    • Synchronous Serial Interface to External Signal Processors, Data Converters, and Logic
    • Slave or Master Mode Operation With Sampling Rates Up to 216 kHz
    • Supports Left-Justified, Right-Justified, and Philips I2S™ Data Formats
    • Supports Audio Data Word Lengths Up to
      24 Bits
  • Four General-Purpose Digital Outputs
    • Multifunction Programmable Through Control Registers
  • Extensive Power-Down Support
    • Functional Blocks May Be Disabled Individually When Not In Use
  • Operates From 1.8-V Core and 3.3-V I/O Power Supplies
  • Small TQFP-48 Package, Compatible With the SRC4382 and SRC4392

2 Applications

  • Digital Audio Recorders and Mixing Desks
  • Digital Audio Interfaces for Computers
  • Digital Audio Routers and Distribution Systems
  • Broadcast Studio Equipment
  • DVD and CD Recorders
  • Surround Sound Decoders and A/V Receivers
  • Car Audio Systems

3 Description

The DIX4192 device is a highly-integrated CMOS device designed for use in professional and broadcast digital audio systems. The DIX4192 combines a digital audio interface receiver (DIR) and transmitter (DIT), two audio serial ports, and flexible distribution logic for interconnection of the function block data and clocks.

The DIR and DIT are compatible with the AES3, S/PDIF, IEC 60958, and EIAJ CP-1201 interface standards. The audio serial ports and DIT may be operated at sampling rates up to 216 kHz. The DIR lock range includes sampling rates from 20 kHz to 216 kHz.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DIX4192 TQFP (48) 7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

DIX4192 Typical Application

DIX4192 typ_app_dix4192.gif

4 Revision History

Changes from E Revision (April 2016) to F Revision

  • Changed fMCLK Max value From: 2.27 To: 27.7 Go

Changes from D Revision (January 2016) to E Revision

  • Changed "IIH High-level input current" MAX value From: 10 µA To: 25 µA in the Electrical Characteristics tableGo
  • Changed Byte 2 in Figure 22a) Current Address Read, .. Go

Changes from C Revision (June 2006) to D Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go

5 Description (continued)

The DIX4192 device is configured using on-chip control registers and data buffers, which are accessed through either a 4-wire serial peripheral interface (SPI) port, or a 2-wire Philips I2C bus interface. Status registers provide access to a variety of flag and error bits, which are derived from the various function blocks. An open-drain interrupt output pin is provided, and is supported by flexible interrupt reporting and mask options through control register settings. A master reset input pin is provided for initialization by a host processor or supervisory functions.

The DIX4192 device requires a 1.8-V core logic supply, in addition to a 3.3-V supply for powering portions of the DIR, DIT, and line driver and receiver functions. A separate logic I/O supply supports operation from 1.65 V to 3.6 V, providing compatibility with low voltage logic interfaces typically found on digital signal processors and programmable logic devices. The DIX4192 device is available in a lead-free, TQFP-48 package, and is pin- and register-compatible with the Texas Instruments SRC4382 and SRC4392 products.

6 Device Comparison Table

PART NUMBER 1.8 V IO MULTI-CH PCM ADC PCM PORTS S/PDIF PORTS
DIX4192 Yes No No 2 4 differential Line IN and 1 differential Line Out
PCM9211 No Yes Yes Up to 3 IN and up to 3 Out Up to 12 single-ended IN and up to 2 single-ended Out
DIX9211 No Yes No Up to 3 IN and up to 3 Out Up to 12 single-ended IN and up to 2 single-ended Out

7 Pin Configuration and Functions

PFB Package
48-Pin TQFP
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
AESOUT 34 O DIT buffered AES3-encoded data
AGND 10 GND DIR comparator and PLL power-supply ground
BCKA 37 I/O Audio serial Port A bit clock
BCKB 48 I/O Audio serial Port B bit clock
BGND 44 GND Substrate ground, connect to AGND (pin 10)
BLS 35 I/O DIT block start clock
CCLK or SCL 20 I Serial data clock for SPI mode or I2C mode
CDIN or A1 21 I SPI port serial data input or programmable slave address for I2C mode
CDOUT or SDA 22 I/O SPI port serial data output (tri-state output) or serial data I/O for I2C mode
CPM 18 I Control port mode, 0 = SPI mode, 1 = I2C mode
CS or A0 19 I Chip select (active low) for SPI mode or programmable slave address for I2C mode
DGND1 16 GND Digital core ground
DGND2 30 GND DIR line receiver bias and DIT line driver digital ground
DGND3 43 GND Logic I/O ground
GPO1 26 O General-purpose output 1
GPO2 27 O General-purpose output 2
GPO3 28 O General-purpose output 3
GPO4 29 O General-purpose output 4
INT 23 O Interrupt flag (open-drain, active low)
LOCK 11 O DIR PLL lock flag (active low)
LRCKA 38 I/O Audio serial Port A Left/Right clock
LRCKB 47 I/O Audio serial Port B left/right clock
MCLK 25 I Master clock
NC 14, 15, 41 — No internal signal connection, internally bonded to ESD pad
RST 24 I Reset (active low)
RX1+ 1 I Line receiver 1, noninverting input
RX1– 2 I Line receiver 1, inverting input
RX2+ 3 I Line receiver 2, noninverting input
RX2– 4 I Line receiver 2, inverting input
RX3+ 5 I Line receiver 3, noninverting input
RX3– 6 I Line receiver 3, inverting input
RX4+ 7 I Line receiver 4, noninverting input
RX4– 8 I Line receiver 4, inverting input
RXCKI 13 I DIR reference clock
RXCKO 12 O DIR recovered master clock (tri-state output)
SDINA 39 I Audio serial Port A data input
SDINB 46 I Audio serial Port B data input
SDOUTA 40 O Audio serial Port A data output
SDOUTB 45 O Audio serial Port B data output
SYNC 36 O DIT internal sync clock
TX+ 32 O DIT line driver noninverting output
TX– 31 O DIT line driver inverting output
VCC 9 PWR DIR comparator and PLL power supply, 3.3-V nominal
VDD18 17 PWR Digital core supply, 1.8-V nominal
VDD33 33 PWR DIR line receiver bias and DIT line driver supply, 3.3-V nominal
VIO 42 PWR Logic I/O supply, 1.65 V to 3.6 V
(1) I = Input, O = Output, PWR = Power, GND = Ground

 
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