The DIX4192 device is a highly-integrated CMOS device designed for use in professional and broadcast digital audio systems. The DIX4192 combines a digital audio interface receiver (DIR) and transmitter (DIT), two audio serial ports, and flexible distribution logic for interconnection of the function block data and clocks.
The DIR and DIT are compatible with the AES3, S/PDIF, IEC 60958, and EIAJ CP-1201 interface standards. The audio serial ports and DIT may be operated at sampling rates up to 216 kHz. The DIR lock range includes sampling rates from 20 kHz to 216 kHz.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DIX4192 | TQFP (48) | 7.00 mm × 7.00 mm |
Changes from E Revision (April 2016) to F Revision
Changes from D Revision (January 2016) to E Revision
Changes from C Revision (June 2006) to D Revision
The DIX4192 device is configured using on-chip control registers and data buffers, which are accessed through either a 4-wire serial peripheral interface (SPI) port, or a 2-wire Philips I2C bus interface. Status registers provide access to a variety of flag and error bits, which are derived from the various function blocks. An open-drain interrupt output pin is provided, and is supported by flexible interrupt reporting and mask options through control register settings. A master reset input pin is provided for initialization by a host processor or supervisory functions.
The DIX4192 device requires a 1.8-V core logic supply, in addition to a 3.3-V supply for powering portions of the DIR, DIT, and line driver and receiver functions. A separate logic I/O supply supports operation from 1.65 V to 3.6 V, providing compatibility with low voltage logic interfaces typically found on digital signal processors and programmable logic devices. The DIX4192 device is available in a lead-free, TQFP-48 package, and is pin- and register-compatible with the Texas Instruments SRC4382 and SRC4392 products.
PART NUMBER | 1.8 V IO | MULTI-CH PCM | ADC | PCM PORTS | S/PDIF PORTS |
---|---|---|---|---|---|
DIX4192 | Yes | No | No | 2 | 4 differential Line IN and 1 differential Line Out |
PCM9211 | No | Yes | Yes | Up to 3 IN and up to 3 Out | Up to 12 single-ended IN and up to 2 single-ended Out |
DIX9211 | No | Yes | No | Up to 3 IN and up to 3 Out | Up to 12 single-ended IN and up to 2 single-ended Out |
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AESOUT | 34 | O | DIT buffered AES3-encoded data |
AGND | 10 | GND | DIR comparator and PLL power-supply ground |
BCKA | 37 | I/O | Audio serial Port A bit clock |
BCKB | 48 | I/O | Audio serial Port B bit clock |
BGND | 44 | GND | Substrate ground, connect to AGND (pin 10) |
BLS | 35 | I/O | DIT block start clock |
CCLK or SCL | 20 | I | Serial data clock for SPI mode or I2C mode |
CDIN or A1 | 21 | I | SPI port serial data input or programmable slave address for I2C mode |
CDOUT or SDA | 22 | I/O | SPI port serial data output (tri-state output) or serial data I/O for I2C mode |
CPM | 18 | I | Control port mode, 0 = SPI mode, 1 = I2C mode |
CS or A0 | 19 | I | Chip select (active low) for SPI mode or programmable slave address for I2C mode |
DGND1 | 16 | GND | Digital core ground |
DGND2 | 30 | GND | DIR line receiver bias and DIT line driver digital ground |
DGND3 | 43 | GND | Logic I/O ground |
GPO1 | 26 | O | General-purpose output 1 |
GPO2 | 27 | O | General-purpose output 2 |
GPO3 | 28 | O | General-purpose output 3 |
GPO4 | 29 | O | General-purpose output 4 |
INT | 23 | O | Interrupt flag (open-drain, active low) |
LOCK | 11 | O | DIR PLL lock flag (active low) |
LRCKA | 38 | I/O | Audio serial Port A Left/Right clock |
LRCKB | 47 | I/O | Audio serial Port B left/right clock |
MCLK | 25 | I | Master clock |
NC | 14, 15, 41 | — | No internal signal connection, internally bonded to ESD pad |
RST | 24 | I | Reset (active low) |
RX1+ | 1 | I | Line receiver 1, noninverting input |
RX1– | 2 | I | Line receiver 1, inverting input |
RX2+ | 3 | I | Line receiver 2, noninverting input |
RX2– | 4 | I | Line receiver 2, inverting input |
RX3+ | 5 | I | Line receiver 3, noninverting input |
RX3– | 6 | I | Line receiver 3, inverting input |
RX4+ | 7 | I | Line receiver 4, noninverting input |
RX4– | 8 | I | Line receiver 4, inverting input |
RXCKI | 13 | I | DIR reference clock |
RXCKO | 12 | O | DIR recovered master clock (tri-state output) |
SDINA | 39 | I | Audio serial Port A data input |
SDINB | 46 | I | Audio serial Port B data input |
SDOUTA | 40 | O | Audio serial Port A data output |
SDOUTB | 45 | O | Audio serial Port B data output |
SYNC | 36 | O | DIT internal sync clock |
TX+ | 32 | O | DIT line driver noninverting output |
TX– | 31 | O | DIT line driver inverting output |
VCC | 9 | PWR | DIR comparator and PLL power supply, 3.3-V nominal |
VDD18 | 17 | PWR | Digital core supply, 1.8-V nominal |
VDD33 | 33 | PWR | DIR line receiver bias and DIT line driver supply, 3.3-V nominal |
VIO | 42 | PWR | Logic I/O supply, 1.65 V to 3.6 V |