DLPS180C may   2020  – july 2023 DLP2010LC

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
    14. 6.14 Software Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Optical Interface and System Image Quality
        1. 7.5.1.1 Numerical Aperture and Stray Light Control
        2. 7.5.1.2 Pupil Match
        3. 7.5.1.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Power Density Calculation
    8. 7.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.8.1 Definition of Micromirror Landed-On and Landed-Off Duty Cycle
      2. 7.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1.      46
      2. 8.2.1 Design Requirements
      3. 8.2.2 Detailed Design Procedure
      4. 8.2.3 Application Curve
  10. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-CFC3FEBD-C748-4CD6-8242-7BB9EC5E6AFE-low.gif Figure 5-1 FQJ Package40-Pin ConnectorBottom View
Table 5-1 Pin Functions – Connector Pins
PIN(1) TYPE SIGNAL DATA RATE DESCRIPTION PACKAGE NET LENGTH(2) (mm)
NAME NO.
DATA INPUTS
D_N(0) G4 I SubLVDS Double Data, Negative 7.03
D_P(0) G3 I SubLVDS Double Data, Positive 7.03
D_N(1) G8 I SubLVDS Double Data, Negative 7.03
D_P(1) G7 I SubLVDS Double Data, Positive 7.03
D_N(2) H5 I SubLVDS Double Data, Negative 7.02
D_P(2) H6 I SubLVDS Double Data, Positive 7.02
D_N(3) H1 I SubLVDS Double Data, Negative 7.00
D_P(3) H2 I SubLVDS Double Data, Positive 7.00
DCLK_N H9 I SubLVDS Double Clock, Negative 7.03
DCLK_P H10 I SubLVDS Double Clock, Positive 7.03
CONTROL INPUTS
DMD_DEN_ARSTZ G12 I LPSDR(1) Asynchronous reset DMD signal. A low signal places the DMD in reset. A high signal releases the DMD from reset and places it in active mode. 5.72
LS_CLK G19 I LPSDR Single Clock for low-speed interface 3.54
LS_WDATA G18 I LPSDR Single Write data for low-speed interface 3.54
LS_RDATA G11 O LPSDR Single Read data for low-speed interface 8.11
POWER
VBIAS(3) H17 Power Supply voltage for positive bias level at micromirrors
VOFFSET(3) H13 Power Supply voltage for HVCMOS core logic.
Includes: supply voltage for stepped high level at micromirror address electrodes and supply voltage for offset level at micromirrors
VRESET(3) H18 Power Supply voltage for negative reset level at micromirrors
VDD(3) G20 Power Supply voltage for micromirror low voltage CMOS core logic includes supply voltage for LPSDR inputs and supply voltage for normal high level at micromirror address electrodes.
VDD H14 Power
VDD H15 Power
VDD H16 Power
VDD H19 Power
VDD H20 Power
VDDI(3) G1 Power Supply voltage for SubLVDS receivers
VDDI G2 Power
VDDI G5 Power
VDDI G6 Power
VSS(3) G9 Ground Ground. Common return for all power.
VSS G10 Ground
VSS G13 Ground
VSS G14 Ground
VSS G15 Ground
VSS G16 Ground
VSS G17 Ground
VSS H3 Ground
VSS H4 Ground
VSS H7 Ground
VSS H8 Ground
VSS H11 Ground
VSS H12 Ground
(1) Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.
(2) Net trace lengths inside the package:
Relative dielectric constant for the FQJ ceramic package is 9.8.
Propagation speed = 11.8 / sqrt(9.8) = 3.769 inches/ns.
Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm.
(3) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.
Table 5-2 Pin Functions – Test Pads
NUMBER SYSTEM BOARD NUMBER SYSTEM BOARD
A2 Do not connect D2 Do not connect
A3 Do not connect D3 Do not connect
A4 Do not connect D17 Do not connect
A5 Do not connect D18 Do not connect
A6 Do not connect
A7 Do not connect E2 Do not connect
A8 Do not connect E3 Do not connect
A9 Do not connect E17 Do not connect
A10 Do not connect E18 Do not connect
A11 Do not connect
A12 Do not connect F1 Do not connect
A13 Do not connect F2 Do not connect
A14 Do not connect F3 Do not connect
A15 Do not connect F4 Do not connect
A16 Do not connect F5 Do not connect
A17 Do not connect F6 Do not connect
A18 Do not connect F7 Do not connect
A19 Do not connect F8 Do not connect
F9 Do not connect
B2 Do not connect F10 Do not connect
B3 Do not connect F11 Do not connect
B17 Do not connect F12 Do not connect
B18 Do not connect F13 Do not connect
F14 Do not connect
C2 Do not connect F15 Do not connect
C3 Do not connect F16 Do not connect
C17 Do not connect F17 Do not connect
C18 Do not connect F18 Do not connect
F19 Do not connect