DLPS119B December   2018  – May 2022 DLP2010NIR

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
      1. 6.13.1 Software Requirements
    14. 6.14 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Optical Interface and System Image Quality
        1. 7.5.1.1 Numerical Aperture and Stray Light Control
        2. 7.5.1.2 Pupil Match
        3. 7.5.1.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • FQJ|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)(1)(2)

MIN NOM MAX UNIT
SUPPLY VOLTAGE RANGE(3)
VDD Supply voltage for LVCMOS core logic
Supply voltage for LPSDR low-speed interface		 1.65 1.8 1.95 V
VDDI Supply voltage for SubLVDS receivers 1.65 1.8 1.95 V
VOFFSET Supply voltage for HVCMOS and micromirror electrode(4) 9.5 10 10.5 V
VBIAS Supply voltage for mirror electrode 17.5 18 18.5 V
VRESET Supply voltage for micromirror electrode –14.5 –14 –13.5 V
|VDDI–VDD| Supply voltage delta (absolute value)(5) 0.3 V
|VBIAS–VOFFSET| Supply voltage delta (absolute value)(6) 10.5 V
|VBIAS–VRESET| Supply voltage delta (absolute value)(7) 33 V
OUTPUT TERMINALS
IOH High-level output current at Voh = 0.8 × VDD –30 mA
IOL Low-level output current at Vol = 0.2 × VDD 30 mA
CLOCK FREQUENCY
ƒclock Clock frequency for low speed interface LS_CLK(8) 108 120 MHz
ƒclock Clock frequency for high speed interface DCLK(9) 300 600 MHz
Duty cycle distortion DCLK 44% 56%
SUBLVDS INTERFACE(9)
|VID| SubLVDS input differential voltage (absolute value) Figure 6-8, Figure 6-9 150 250 350 mV
VCM Common mode voltage Figure 6-8, Figure 6-9 700 900 1100 mV
VSUBLVDS SubLVDS voltage Figure 6-8, Figure 6-9 575 1225 mV
ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω
ZIN Internal differential termination resistance Figure 6-10 80 100 120 Ω
100-Ω differential PCB trace 6.35 152.4 mm
LPSDR INTERFACE(10)
ZLINE Line differential impedance (PWB/trace) 61.2 68 74.8 Ω
ENVIRONMENTAL
TARRAY Array temperature – long-term operational(11) (12) (13) 0 40 to 70(11) °C
Array temperature – short-term operational, 25 hr max(13)(14) –20 -10
Array temperature – short-term operational, 500hr max (13)(14) -10 0
Array temperature – short-term operational, 500hr max (13)(14) 70 75
TWINDOW Window temperature – operational(15) (17) 90 °C
|TDELTA| Absolute temperature difference between any point on the window edge and the ceramic test point TP1(16) 15 °C
CTELR Cumulative time in elevated dew point temperature range 6 Months
ILLUV Illumination, wavelength < 420 nm 0.68 mW/cm2
ILLVIS Illumination wavelengths between 420 nm and 700 nm Thermally limited
ILLNIR Illumination, wavelength 700 - 2500 nm 2000 mW/cm2
ILLIR Illumination, wavelength > 2500 nm 10 mW/cm2
ILLθ Illumination marginal ray angle(17) 55 deg
(1) Recommended Operating Conditions are applicable after the DMD is installed in the final product.
(2) The functional performance of the device specified in this datasheet is achieved when operating the device within the limits defined by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the Recommended Operating Conditions limits.
(3) All voltage values are with respect to the ground pins (VSS).
(4) VOFFSET supply transients must fall within specified max voltages.
(5) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.
(6) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.
(7) To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than the specified limit.
(8) LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.
(9) Refer to the SubLVDS timing requirements in Section 6.7.
(10) Refer to the LPSDR timing requirements in Section 6.7.
(11) Per Figure 6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Section 7.7 for a definition of micromirror landed duty cycle.
(12) Long-term is defined as the usable life of the device.
(13) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in Figure 7-1 and the package thermal resistance using Section 7.6.
(14) Short-term is the total cumulative time over the useful life of the device.
(15) Window temperature is the highest temperature on the window edge shown in Figure 7-1. The locations of thermal test points TP2 and TP3 in Figure 7-1 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, a test point should be added to that location.
(16) Temperature delta is the highest difference from the ceramic test point 1 (TP1) and anywhere on the window edge shown in Figure 7-1. The window test points TP2 and TP3 shown in Figure 7-1 are intended to result in the worst case delta temperature. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.
(17) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors (POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) will contribute to thermal limitations described in this document, and may negatively affect lifetime.
GUID-A5BFF531-BB66-45CD-A3DF-380AD120C945-low.gif Figure 6-1 Maximum Recommended Array Temperature – Derating Curve